Selective Graphene Growth on Semiconductor Surfaces for Low Resistance
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Solution Overview
Problem
Existing semiconductor devices face challenges in preventing resistance increase due to reduced metal wiring widths and require effective barrier materials, with conventional methods struggling to accurately form graphene layers on desired regions and being prone to residue and oxide formation.
Innovation Solution
A semiconductor device is developed with a graphene layer grown directly on a semiconductor substrate using a plasma-enhanced chemical vapor deposition (PECVD) process, selectively forming the graphene layer only on the semiconductor surface, avoiding the insulator and allowing for precise control over growth time to achieve desired thickness and region specificity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form graphene layers, then graphene can be formed on substrate surfaces, but the graphene layers cannot be accurately formed on desired regions and residue and oxide formation occur
Solution Approach 1:
The patent applies local quality by making the substrate surface have different properties in different regions. The insulator regions and semiconductor regions are treated differently during the graphene formation process, allowing graphene to selectively grow only on desired semiconductor regions while preventing growth on insulator regions. This resolves the contradiction by enabling precise regional control without residue formation.
Solution Approach 2:
The patent applies preliminary action by performing surface treatment or patterning of the substrate before the graphene formation process. By pre-defining the regions where graphene should form (through insulator placement or surface modification), the subsequent graphene deposition occurs only in predetermined areas, achieving high manufacturing precision and preventing harmful residue formation.
2Area of moving object
If metal wiring width is reduced to increase integration density, then device miniaturization is achieved, but resistance increases
Solution Approach 1:
The patent applies composite materials by combining graphene with existing semiconductor structures. Graphene, with its superior electrical conductivity, is integrated into the metal wiring system to create a composite conductive path. This allows the wiring to maintain low resistance even when the overall width is reduced, as the graphene component compensates for the increased resistance that would normally result from smaller cross-sections.
Solution Approach 2:
The patent applies parameter changes by introducing a new material (graphene) with different electrical properties into the wiring system. Graphene's high electron mobility and conductivity fundamentally change the electrical parameters of the wiring structure, enabling reduced dimensions without the associated resistance penalty that would occur with conventional metals alone.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of a semiconductor device with a graphene layer that effectively addresses resistance issues by selectively growing graphene on the semiconductor surface, improving precision and reducing residue and oxide formation, thus enhancing device performance.
Implementation Method 1
a graphene layer grown directly on a semiconductor substrate using a plasma-enhanced chemical vapor deposition (PECVD) process
Data Source
AI summary
Provided is a semiconductor device including graphene. The semiconductor device includes: a substrate including an insulator and a semiconductor; and a graphene layer configured to directly grow only on a surface of the semiconductor, wherein the semiconductor includes at least one of a group IV material and a group III-V compound.