Selective High-K Gate Dielectric Formation in Replacement Gates
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Solution Overview
Problem
The increasing miniaturization of integrated circuits makes it challenging to accommodate multiple sub-layers in replacement gates, particularly due to the difficulty in forming high-k gate dielectrics on the sidewalls of gate spacers without increasing parasitic capacitance.
Innovation Solution
A method is introduced to selectively form an inhibitor film on the sidewalls of gate spacers, preventing the growth of high-k gate dielectrics on these surfaces, which allows for the selective deposition of high-k gate dielectrics only on the semiconductor fins, thereby reducing parasitic capacitance and facilitating the formation of replacement gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k gate dielectrics are formed on sidewalls of gate spacers, then gate dielectric coverage is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by selectively depositing high-k gate dielectric material only on specific surfaces (semiconductor fins) while excluding other surfaces (gate spacer sidewalls) through spatially selective deposition processes. This ensures gate dielectric coverage is provided where needed for reliability while preventing parasitic capacitance formation where it would be harmful.
Solution Approach 2:
The patent extracts or removes the gate spacer sidewall surfaces from the deposition process using masking techniques, preventing high-k dielectric material from depositing on these surfaces. This extraction of problematic surfaces from the deposition zone eliminates the source of parasitic capacitance while maintaining necessary dielectric coverage on fin surfaces.
2Adaptability or versatility
If multiple sub-layers are accommodated in replacement gates, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming gate spacers and selectively preparing surfaces before depositing high-k gate dielectric material. This preliminary surface preparation and selective masking enables subsequent straightforward deposition of multiple sub-layers without requiring complex in-situ manipulation, reducing overall manufacturing complexity while maintaining device functionality.
Solution Approach 2:
The patent segments the gate structure formation into distinct steps: forming gate spacers, selective surface preparation, high-k dielectric deposition on fins only, and subsequent gate electrode formation. This segmentation allows each step to be optimized independently, accommodating multiple sub-layers with improved clarity and reduced manufacturing complexity.
3Length of moving object
If gate dimensions are reduced for miniaturization, then circuit density is improved, but layer accommodation becomes more difficult
Solution Approach 1:
The patent applies local quality by providing gate dielectric coverage only on the fin surfaces where it is electrically necessary, while leaving gate spacer sidewalls uncovered. This localized approach reduces the total amount of dielectric material and simplifies the layer structure in miniaturized devices, making layer accommodation easier while maintaining circuit density improvements from gate shrinkage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces parasitic capacitance and simplifies the formation of replacement gate electrodes by ensuring high-k gate dielectrics are only formed on the semiconductor fins, addressing the challenges of miniaturization and layer accommodation in integrated circuits.
Implementation Method 1
selectively depositing a high-k dielectric layer over and contacting the dielectric interfacial layer, wherein the high-k dielectric layer, as deposited, is free from portions on sidewalls of the gate spacers
Data Source
AI summary
A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.