Selective In-Situ Retouching of Nonvolatile Memory Cells
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Solution Overview
Problem
Non-volatile charge-storage memory systems, such as flash memory, face data disturbance due to charge leakage, leading to misreading of data stored in memory cells, which is not efficiently managed by existing technologies.
Innovation Solution
A method is introduced to perform a retouching operation on memory cells with bad bits by increasing their threshold voltages using small voltage pulses, without erasing the cells, using Error Correction Code (ECC) decoding to identify and correct bad bits, and applying programming pulses only to cells with significant threshold voltage drops, thereby maintaining data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data copying is performed to maintain data integrity, then data reliability is improved, but time consumption and energy usage increase
Solution Approach 1:
The patent extracts only the problematic memory cells containing bad bits and applies retouching operations selectively to these cells rather than performing full data copying across the entire memory array. This targeted approach maintains data reliability for affected cells while minimizing time and energy consumption by excluding unaffected cells from the maintenance operation.
Solution Approach 2:
The patent applies local quality by differentiating between memory cells that require retouching (those with bad bits) and those that do not. The retouching operation is applied locally to only the subset of cells with threshold voltage drops, rather than uniformly across all cells. This selective local treatment maintains data integrity where needed while avoiding unnecessary operations elsewhere.
2Reliability
If full data copying is performed, then data reliability is improved, but energy consumption increases
Solution Approach 1:
The patent extracts only the problematic memory cells containing bad bits and applies retouching operations selectively to these cells rather than performing full data copying across the entire memory array. This targeted approach maintains data reliability for affected cells while minimizing time and energy consumption by excluding unaffected cells from the maintenance operation.
Solution Approach 2:
The patent applies partial action by performing retouching operations on only the subset of memory cells that actually require it (those with bad bits and threshold voltage drops), rather than applying the operation universally to all cells. This partial treatment achieves sufficient data reliability for affected cells without the excessive energy consumption of full-array operations.
3Reliability
If memory cells are erased and reprogrammed, then data integrity is maintained, but device complexity and operation time increase
Solution Approach 1:
Instead of the conventional approach of erasing and reprogramming entire blocks or pages, the patent inverts the approach by applying small retouching pulses directly to individual cells with bad bits to restore their threshold voltages. This inverted approach maintains data integrity without requiring complex erase-and-reprogram operations, thereby reducing device complexity and operation time.
Solution Approach 2:
The patent segments the memory array into individual cells that can be independently identified and treated. By identifying and isolating only the cells with bad bits and applying retouching operations to these specific segments, the system avoids the complexity of erasing and reprogramming entire blocks or pages, thus reducing overall operation complexity.
4Reliability
If retouching is applied to all memory cells, then data reliability is improved, but productivity decreases due to unnecessary operations
Solution Approach 1:
The patent applies local quality by differentiating between memory cells that require retouching (those with bad bits) and those that do not. The retouching operation is applied locally to only the subset of cells with threshold voltage drops, rather than uniformly across all cells. This selective local treatment maintains data integrity where needed while avoiding unnecessary operations elsewhere.
Solution Approach 2:
The patent applies partial action by performing retouching operations on only the subset of memory cells that actually require it (those with bad bits and threshold voltage drops), rather than applying the operation universally to all cells. This partial treatment achieves sufficient data reliability for affected cells without the excessive energy consumption of full-array operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the number of bad bits by restoring threshold voltages to their target ranges, ensuring accurate data reading and reducing the need for data copying or erasure, thus saving time, energy, and space.
Implementation Method 1
Both utilize a floating (unconnected) conductive gate, in a field effect transistor structure, positioned over a channel region in a semiconductor substrate, between source and drain regions. The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate.
Data Source
AI summary
In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge.