Selective Instruction Flushing in Microprocessor Pipelines

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Solution Overview

Problem

Microprocessors face challenges in accurately identifying and tracking branch prediction dependencies in instruction pipelines, leading to inefficiencies in flushing instructions due to branch mispredictions, particularly in superscalar processors with out-of-order execution, where instructions may depend on multiple outstanding predictions.

Innovation Solution

A method and apparatus for managing instruction flushing by marking instructions with branch prediction dependencies using bit indicators, branch flush tags, and branch path tags, allowing for selective flushing of instructions dependent on incorrect branch predictions, and clearing indicators for correct predictions to reuse them.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all instructions are flushed from the pipeline when a branch misprediction is detected, then the correctness of pipeline execution is maintained, but performance and efficiency are lost due to flushing valid instructions

Engineering Contradiction:
Improveexecution correctnessVSAvoidpipeline performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the instruction pipeline into groups based on branch prediction dependencies. Each instruction is tagged with identifiers indicating which branch predictions it depends on, allowing the system to selectively flush only the affected segments rather than the entire pipeline. This segmentation enables precise control over which instructions are invalidated when a misprediction occurs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating instructions differently based on their specific branch dependency characteristics. Instructions are marked with unique identifiers that reflect their local dependency relationships with branch predictions. When a misprediction is detected, only instructions with matching identifiers are flushed, while other instructions continue execution without interruption.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If instructions are tracked with detailed branch prediction dependencies, then selective flushing accuracy is improved, but tracking complexity increases

Engineering Contradiction:
Improvedependency identification accuracyVSAvoidtracking complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent uses copying by creating simplified tag identifiers that represent branch prediction dependencies. Instead of tracking full dependency relationships, the system creates compact tag copies that can be easily attached to instructions and compared during flushing operations. These tags are generated by copying and combining branch prediction identifiers, providing an efficient representation of dependency relationships.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent transforms complex dependency relationships into simple parameter changes by using bit fields and identifiers. Each branch prediction is assigned a unique identifier, and instructions accumulate these identifiers as parameters. When flushing, the system simply compares these parameters rather than analyzing complex dependency graphs, significantly reducing tracking complexity while maintaining precision.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS7949861B2Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline
Publication Date: 2011.05.24 QUALCOMM INC
  • US7949861B2 patent drawing
  • US7949861B2 patent drawing
  • US7949861B2 patent drawing

AI summary

In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.