Selective Interconnect Caps and Liners for Low-Resistance Scaling
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Solution Overview
Problem
As integrated circuits (ICs) scale to smaller features, challenges arise in metallization of metal interconnects with tight pitches, leading to increased resistance and capacitance, while existing capping materials and techniques with novel liner materials can negatively impact device performance by occupying excessive space and increasing resistance.
Innovation Solution
Employing selective deposition of novel cap and liner materials such as ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, and niobium, individually or in alloys, to encapsulate metal interconnects and metal-silicon interfaces, reducing resistance and maintaining reliability without occupying excessive area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional capping materials and techniques are used to encapsulate metal interconnects, then protection against oxidation and contamination is achieved, but excessive space is occupied and resistance increases
Solution Approach 1:
The patent changes the material parameter by transitioning from conventional capping materials (such as tungsten or cobalt) to novel materials including ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, and niobium, either individually or in alloys. This material substitution enables thinner cap thickness while maintaining protective function, thereby reducing the space occupied and resistance without compromising oxidation and contamination protection
Solution Approach 2:
The patent employs composite material structures by combining novel liner materials with selective capping materials. The liner layer (comprising ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, or niobium) works in conjunction with the cap to provide both protection and space efficiency. This composite approach allows for optimized thickness and material distribution that reduces overall space occupation while maintaining reliability
2Productivity
If interconnect width is scaled down to increase density, then capacity increases, but resistance increases due to reduced metal area
Solution Approach 1:
The patent utilizes parameter changes by implementing ultra-thin liner thicknesses and optimized cap thicknesses of the novel materials. These parameter optimizations allow for maximum metal area within the interconnect structure, thereby minimizing resistance even as interconnect width scales down to increase device density
Solution Approach 2:
The patent applies local quality by positioning the novel liner materials specifically at critical interfaces where they provide maximum benefit with minimum space consumption. The selective deposition ensures that materials are placed only where needed (on metal interconnect surfaces and metal-silicon interfaces), preserving metal area and reducing resistance while maintaining protective and adhesive functions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The selective deposition of these materials results in reduced resistance and improved reliability of IC structures, addressing the challenges of scaling while maintaining performance.
Implementation Method 1
Employing selective deposition of novel cap and liner materials such as ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, and niobium
Data Source
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Figure 2A~2B
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AI summary
Selective metal capping and/or liner materials and processes described herein may enable hermetically encapsulating metal interconnects and metal-silicon interfaces in transistor contacts. In one example, an IC structure includes an interconnect layer with a conductive interconnect that is lined with a ruthenium-based liner, and capped with a selectively deposited cap that includes one or more of ruthenium, molybdenum, tungsten, rhodium, iridium, rhenium, and niobium individually or in an alloy. In another example, an IC structure includes a transistor contact structure with a selectively deposited conductive cap over an interface material, where the conductive cap material is absent or substantially thinner on sidewalls of the contact opening. In one example, the conductive cap material over the Si-metal interface includes one or more of ruthenium, molybdenum, tungsten, rhodium, iridium, platinum, rhenium, cobalt, and niobium individually or in combination.