Selective Metal-Dielectric Interconnect Layers for Sub-20 nm Alignment
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in scaling integrated circuit features due to limitations in lithographic techniques and selective deposition methods, particularly at dimensions below 20 nm, leading to increased resistance-capacitance product and misalignment issues in back-end-of-line processing.
Innovation Solution
The alternating cyclic deposition of thin films, where metals are selectively deposited on metals and dielectrics on dielectrics, allows for precise control of lateral growth and dimensional control of features, eliminating the need for blocking or intermediate etching, and enabling the formation of robust nano interconnect structures with improved electronic performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If lithographic techniques are used for scaling integrated circuit features, then feature size can be reduced, but manufacturing precision deteriorates at dimensions below 20 nm
Solution Approach 1:
The patent divides the feature formation process into multiple alternating deposition cycles, where each cycle deposits a thin layer of material and then performs selective removal. This segmentation allows precise control of lateral growth at each stage, achieving dimensional control below 20 nm that cannot be obtained through single-step lithography.
Solution Approach 2:
The patent employs periodic alternating deposition of different materials (e.g., metal and dielectric layers) in cycles, where each cycle refines the feature dimensions. This periodic action enables progressive dimensional control and alignment precision that overcomes lithographic limitations at sub-20 nm scales.
2Manufacturing precision
If selective deposition methods are used, then lateral growth control is achieved, but device complexity increases due to blocking and intermediate etching requirements
Solution Approach 1:
The patent designs the alternating deposition process where previously deposited layers automatically serve as blocking layers for subsequent selective deposition. The structure self-organizes without requiring external blocking layers or intermediate etching steps, reducing process complexity while maintaining precise lateral growth control.
Solution Approach 2:
The patent performs preliminary alternating deposition cycles that pre-form the structural framework before final feature completion. These preliminary cycles create self-aligned blocking structures and prepare the substrate for subsequent selective deposition, eliminating the need for complex intermediate etching and blocking operations.
3Manufacturing precision
If alternating cyclic deposition is used, then alignment precision is improved, but manufacturing time increases
Solution Approach 1:
The patent merges multiple functions into each alternating deposition cycle: material deposition, self-aligned blocking formation, and lateral growth control all occur within the same cycle. This consolidation achieves high alignment precision while reducing the total number of separate processing steps compared to conventional sequential methods.
Solution Approach 2:
The patent maintains continuous useful action through alternating deposition cycles where each cycle builds upon the previous one without requiring intermediate stopping, blocking, or etching steps. The process flows continuously with each cycle contributing to final alignment precision, reducing idle time and manufacturing cycle time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in fully aligned via structures, enhanced dielectric breakdown, reduced resistance-capacitance, and improved reliability of nanostructures, compatible with current process flows and suitable for advanced conductive nanostructures and interconnects.
Implementation Method 1
metals are selectively deposited on metals and dielectrics are selectively deposited on dielectrics
Data Source
AI summary
A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.