Selective Interconnect Deposition for Self-Aligned Low-k Vias
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Solution Overview
Problem
As integrated circuit interconnect features shrink, they face challenges such as reduced landing areas for vias, increased parasitic capacitance, and sensitivity to overlay errors, leading to potential shorts and line breakdown.
Innovation Solution
The selective deposition of dielectric alignment features above and between conductive features self-aligns vias, reducing parasitic capacitance and overlay errors, while using a low-k dielectric material further minimizes capacitance and enhances the reliability of smaller interconnect features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect features are scaled down to increase functional density, then production efficiency is improved and costs are lowered, but parasitic capacitance increases and reliability deteriorates
Solution Approach 1:
The patent applies different dielectric materials with different k-values to different spatial regions around the conductive line. Specifically, a first dielectric material with a first k-value is placed in a first region, while a second dielectric material with a second k-value (lower than the first) is placed in a second region closer to the conductive line. This local differentiation allows the interconnect structure to maintain overall functionality while reducing parasitic capacitance in the critical region adjacent to the conductor, thereby improving reliability without sacrificing the benefits of scaling.
2Length of stationary object
If interconnect features are scaled down, then geometry size decreases and functional density increases, but parasitic capacitance increases due to reduced spacing
Solution Approach 1:
The patent implements local quality by using a first dielectric material in a first region and a second dielectric material with lower k-value in a second region adjacent to the conductive line. This spatial variation in dielectric properties directly addresses the parasitic capacitance issue by providing low-k material where it is most needed (closest to the conductor) while maintaining structural integrity elsewhere.
Solution Approach 2:
The patent employs composite dielectric structures by combining multiple dielectric materials with different k-values in a single interconnect system. The first dielectric material and second dielectric material form a composite structure that optimizes the balance between electrical performance (reduced parasitic capacitance) and mechanical/structural requirements, enabling continued scaling without proportional increases in parasitic effects.
3Ease of manufacture
If conventional dielectric materials are used in all regions, then manufacturing is simplified, but parasitic capacitance cannot be sufficiently reduced
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through region-specific dielectric material selection. The first dielectric material is used in regions where manufacturing simplicity is acceptable, while the second low-k dielectric material is strategically placed in regions where parasitic capacitance reduction is critical. This approach maintains ease of manufacture for the overall structure while achieving the necessary capacitance reduction through localized material optimization.
Solution Approach 2:
The use of composite dielectric materials allows the patent to balance manufacturing complexity with electrical performance. By combining conventional dielectric materials with low-k materials in specific configurations, the patent achieves reduced parasitic capacitance without requiring a complete overhaul of the manufacturing process, thus maintaining reasonable ease of manufacture while addressing the capacitance issue.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of smaller, more reliable interconnect features with reduced sensitivity to overlay errors and decreased parasitic capacitance, improving the reliability and regularity of interconnect structures in integrated circuits.
Implementation Method 1
using a low-k dielectric material further minimizes capacitance
Data Source
AI summary
Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.