Selective Internal Gate Structure for Capacitance-Matched FeFETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The formation of internal gate structures in ferroelectric semiconductor devices faces challenges such as increased thickness leading to reduced gate contact area, increased contact resistance, parasitic capacitance causing gate leakage, and mismatched capacitances between ferroelectric and high-k capacitors, which degrade device performance.
Innovation Solution
A selectively-grown internal gate structure is formed using a horizontal configuration, involving a seed layer and a metal layer, with controlled etching to match capacitive properties and reduce parasitic capacitance, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer thickness is increased to improve capacitance matching, then the capacitive properties are improved, but the gate contact area is reduced and contact resistance increases
Solution Approach 1:
The gate structure is segmented into multiple components: a gate dielectric layer, an internal gate electrode, and a ferroelectric layer. This segmentation allows the internal gate electrode to be positioned within the gate dielectric layer, effectively dividing the capacitance function between the gate dielectric layer and the ferroelectric layer, thereby achieving capacitance matching without requiring excessive thickness of the gate dielectric layer.
Solution Approach 2:
The internal gate electrode is positioned in the vertical dimension within the gate dielectric layer rather than only in the horizontal plane. This dimensional change allows the gate contact area to be maintained in the horizontal plane while adding capacitance through the vertical positioning of the internal gate electrode within the gate dielectric layer.
2Reliability
If the gate dielectric layer thickness is increased to improve capacitance matching, then the capacitive properties are improved, but gate leakage increases due to parasitic capacitance
Solution Approach 1:
The capacitance function is segmented between the gate dielectric layer and the ferroelectric layer, with the internal gate electrode positioned within the gate dielectric layer. This segmentation allows for precise control of capacitance matching while maintaining proper electrical isolation, thereby reducing parasitic capacitance and gate leakage.
Solution Approach 2:
The internal gate electrode acts as an intermediary element positioned within the gate dielectric layer, mediating the electrical interaction between the gate electrode and the channel. This intermediary structure enables capacitance matching while maintaining electrical isolation and reducing parasitic capacitance effects.
3Device complexity
If a conventional gate structure is used, then the device structure is simpler, but the capacitive mismatch between ferroelectric and high-k capacitors degrades device performance
Solution Approach 1:
The gate structure is segmented into distinct functional components: a gate dielectric layer, an internal gate electrode positioned within it, and a ferroelectric layer. This segmentation enables independent optimization of each component's properties, achieving capacitance matching and improved device performance while maintaining a relatively straightforward fabrication process.
Solution Approach 2:
The gate structure employs a composite configuration combining a gate dielectric layer (high-k material) with a ferroelectric layer and an internal gate electrode. This composite structure leverages the complementary properties of different materials to achieve capacitance matching and improved device performance.
Data Source
AI summary
The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.