Selective IC Layer Transfer Using Offset Bonding Layouts

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Solution Overview

Problem

Current layer transfer techniques in semiconductor manufacturing require full layer transfers, leading to increased costs and process complexity due to the need to etch away unneeded portions of the transferred layer.

Innovation Solution

The use of selective release technology on a donor substrate in conjunction with a patterned bonding template on a receiver substrate allows for the selective transfer of specific areas of a layer, enabling the reuse of the donor substrate and reducing the need for post-transfer etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If full layer transfer is performed, then complete layer coverage is achieved, but material waste and process complexity increase due to required post-transfer etching

Engineering Contradiction:
Improvelayer transfer completenessVSAvoidmaterial waste
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

The patent divides the layer transfer process into discrete transferable units (chips or die) rather than transferring entire layers. This segmentation allows only the needed portions to be transferred to the substrate, eliminating the need to etch away unneeded portions and reducing material waste.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different properties to different regions of the layer - some areas are made transferable while others remain non-transferable. This local differentiation enables selective transfer of only the required regions, avoiding the material waste associated with blanket layer transfer followed by etching.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If full layer transfer is performed, then complete layer coverage is achieved, but process complexity increases due to post-transfer etching steps

Engineering Contradiction:
Improvelayer transfer completenessVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

By segmenting the layer into transferable chip units, the patent eliminates the need for post-transfer etching steps that would be required to remove unneeded portions of a fully transferred layer, thereby simplifying the overall process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary separation of the layer into discrete transferable units before the transfer process. This preliminary action prevents the need for subsequent etching operations, reducing process complexity.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If non-selective layer transfer is used, then transfer process is simpler, but donor substrate cannot be reused increasing costs

Engineering Contradiction:
Improvetransfer process simplicityVSAvoiddonor substrate reuse capability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent segments the layer into discrete chips that can be selectively transferred, leaving the remaining donor substrate intact and reusable. This segmentation approach maintains relative process simplicity while enabling donor substrate reuse.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent enables recovery and reuse of the donor substrate by transferring only specific chips to the substrate and leaving the rest of the donor substrate intact for subsequent transfer cycles, thereby reducing costs.

Inventive Principle:
Principle #34Discarding and recovering

Data Source

PatentUS20250112218A1Selective layer transfer process improvements
Publication Date: 2025.04.03 INTEL CORP
  • US20250112218A1 patent drawing
  • US20250112218A1 patent drawing
  • US20250112218A1 patent drawing

AI summary

In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. The process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of IC components on the first substrate to respective bonding structures on the third substrate.