Selective LDD Implant Layout With Diffusion Suppression in CMOS
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Solution Overview
Problem
As semiconductor devices evolve with smaller critical dimensions, controlling implant profiles for transistors with lightly doped drain (LDD) implants and those without becomes increasingly difficult, especially when integrating complementary metal oxide semiconductor (CMOS) devices and analog devices on the same substrate.
Innovation Solution
The introduction of a semiconductor device design that includes a first transistor with an LDD region and a diffusion suppressant region, and a second transistor without an LDD region or diffusion suppressant region, allowing for concurrent formation of source/drain regions. This approach utilizes a photolithography operation to selectively apply LDD and diffusion suppression implants only to the first transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDD implants and diffusion suppressant implants are applied to all transistors, then short channel effects are reduced, but resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent applies LDD implants and diffusion suppressant implants selectively only to core transistors that require short channel effect control, while leaving I/O transistors without these implants. This local differentiation allows each transistor type to have optimized characteristics appropriate to its function, reducing unnecessary manufacturing complexity while maintaining reliability where needed.
Solution Approach 2:
The patent segments the transistor population into two distinct groups: core transistors receiving LDD and diffusion suppressant implants, and I/O transistors receiving neither. This segmentation allows independent optimization of each group's electrical characteristics and simplifies the manufacturing process by avoiding universal application of complex implantation sequences.
2Reliability
If LDD implants are applied to reduce drain induced barrier lowering, then transistor performance improves, but source/drain diffusion increases and manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a diffusion suppressant implant as an intermediary layer between the LDD implant and the source/drain regions. This diffusion suppressant acts as a barrier that allows LDD implants to reduce drain induced barrier lowering while preventing excessive source/drain diffusion, thereby relaxing manufacturing precision requirements.
Solution Approach 2:
The diffusion suppressant implant is applied in advance to prevent harmful diffusion before it occurs. By placing this suppressant layer prior to source/drain formation, the patent preemptively counteracts the diffusion that would otherwise require tighter process control.
3Adaptability or versatility
If different implant profiles are used for core and I/O transistors, then performance metrics are optimized for each type, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the manufacturing processes for core and I/O transistors into a single unified sequence. By applying LDD and diffusion suppressant implants to all transistors simultaneously using blanket wafers, then selectively removing suppressant material from I/O regions, the patent achieves different final profiles without requiring separate processing lines or complex masking for each transistor type.
Solution Approach 2:
The patent performs preliminary implantation of LDD and diffusion suppressant materials to all transistors before differentiating between core and I/O devices. This preliminary action allows subsequent selective removal of suppressant material from I/O regions, achieving customized profiles through a simplified two-stage process rather than complex selective implantation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables effective integration of transistors with different characteristics on the same substrate, minimizing diffusion of source/drain implants in the first transistor to reduce drain induced barrier lowering and short channel effects, while allowing more diffusion in the second transistor to lower resistance, thus meeting specific performance metrics for each type of transistor.
Implementation Method 1
a diffusion suppressant region with a diffusion suppressant species partially or completely overlapping the LDD region
Data Source
AI summary
The present disclosure provides a method for forming a semiconductor device containing MOS transistors both with and without source/drain extension regions in a semiconductor substrate having a semiconductor material on either side of a gate structure including a gate electrode on a gate dielectric formed in a semiconductor material. In devices with source/drain extensions, a diffusion suppression species of one or more of indium, carbon and a halogen are used. The diffusion suppression implant can be selectively provided only to the semiconductor devices with drain extensions while devices without drain extensions remain diffusion suppression implant free.