Selective Liner Etching for Dual Epitaxial Source/Drain FinFETs
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Solution Overview
Problem
Current dual epitaxial processes for forming raised source/drain regions in finFET CMOS devices are challenging due to the need for multiple wet etch operations, which can inadvertently attack isolation regions, leading to undercutting and device damage.
Innovation Solution
A method involving the use of first and second angled ions to create altered liner layers with enhanced etch rates, allowing for selective removal of liner layers and reduced etch times, thereby minimizing the impact on isolation regions during epitaxial source/drain growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple wet etch operations are performed to remove liners in PFET and NFET regions, then the liner layers are completely removed to enable epitaxial growth, but the isolation regions are inadvertently attacked and undercut
Solution Approach 1:
The patent applies local quality by creating a selectively altered liner layer with different etch resistance properties in different regions. The first altered liner layer is formed in PFET region liners through angled ion exposure, making them more susceptible to etching, while NFET region liners remain unaltered and resistant to etching. This spatial differentiation of liner properties enables selective removal in specific regions without affecting isolation structures elsewhere.
Solution Approach 2:
The patent employs preliminary action by pre-altering the liner layer properties before the etching process. The angled ion exposure modifies the chemical composition or structure of the liner material in advance, creating a liner layer that etches at a different rate. This preliminary modification ensures that when the wet etch is applied, the altered liner removes selectively while protecting the isolation regions from undercutting.
2Manufacturing precision
If longer etch times are used to ensure complete liner removal, then all liner material is removed, but the isolation regions are more severely damaged
Solution Approach 1:
The patent creates local quality differences in the liner layer through selective angled ion exposure. The altered liner layer in exposed regions has enhanced etchability, allowing complete liner removal in those specific areas. The unaltered liner in other regions maintains its original etch resistance, protecting isolation structures even during extended etch times. This spatial variation in liner properties decouples the etch time requirement from isolation region damage.
3Reliability
If shorter etch times are used to protect isolation regions, then isolation regions are preserved, but liner removal may be incomplete
Solution Approach 1:
The patent changes the etch rate parameter of the liner layer through angled ion exposure. The altered liner layer exhibits a different etch rate compared to the unaltered liner, enabling complete removal of the altered portion in a shorter time. This parameter modification allows the etch process to be stopped before isolation regions are damaged, while still achieving complete liner removal in the regions where it is desired.
4Ease of manufacture
If four separate wet etch operations are performed for dual epitaxial scheme, then both PFET and NFET liners are removed, but the process complexity increases and isolation regions are at risk
Solution Approach 1:
The patent merges multiple etch operations into a single unified process by creating spatially differentiated liner properties beforehand. The angled ion exposure selectively alters liners in PFET regions while leaving NFET region liners unaltered. A single wet etch operation then removes only the altered liners, achieving what would have required four separate etch operations, while simultaneously protecting isolation regions from damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of dual epitaxial raised source/drain structures in CMOS finFET devices without undue etching of isolation structures, reducing the risk of gate bending and device loss, while providing a wider process window for liner-removal etching.
Implementation Method 1
directing first angled ions at the transistor structure, wherein a first altered liner layer is created in a first portion of the liner layer
Implementation Method 2
exposing the transistor structure to a liner-removal etchant, wherein the first altered liner layer is removed in the first portion
Implementation Method 3
performing a first epitaxial source/drain growth operation, wherein a first semiconductor material is grown on source/drain regions of the first portion
Data Source
AI summary
A method of forming a three-dimensional transistor device. The method may include providing a transistor structure, where the transistor structure includes a fin assembly, a gate assembly, the gate assembly disposed over the fin assembly and comprising a plurality of gates, a liner layer, disposed over the plurality of gates, and an isolation layer, disposed subjacent the liner layer. The method may also include directing first angled ions at the transistor device, wherein a first altered liner layer is created in the liner layer, wherein, in the presence of a liner-removal etchant, the liner layer exhibits a first etch rate, the first altered liner layer exhibits a second etch rate, greater than the first etch rate.