Selective Memory Bank Refresh Circuit Reduces DRAM Current
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Solution Overview
Problem
Existing semiconductor memory devices, such as DRAMs, face increased current consumption due to the need for a refresh function to prevent data loss, which limits their versatility and universality, especially in mobile electronic devices with high storage capacity demands.
Innovation Solution
A semiconductor memory device with multiple memory banks and refresh control circuits that automatically perform refresh operations only on banks where data has been written, eliminating the need for a special refresh sequence and reducing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operation is performed on all memory banks, then data retention is ensured, but current consumption increases
Solution Approach 1:
The memory system is divided into multiple independent memory banks, each with its own refresh control circuit and holding circuit. This segmentation allows selective refresh of individual banks based on their specific needs, rather than refreshing all banks uniformly, thereby reducing overall current consumption while ensuring data retention in banks that require it.
Solution Approach 2:
Instead of performing refresh operations on all memory banks (excessive action), the system performs refresh operations only on the specific banks that have written data and require refresh (partial action). This is achieved through the holding circuit that tracks which banks need refresh, eliminating unnecessary refresh operations and reducing current consumption.
2Use of energy by moving object
If special refresh sequence is implemented, then current consumption is reduced, but compatibility with general-purpose DRAMs is lost
Solution Approach 1:
The system uses the existing command generation circuit to automatically detect when data has been written to a memory bank and autonomously generates refresh commands for that specific bank. This self-service mechanism eliminates the need for external special refresh sequences while reducing current consumption, maintaining compatibility with general-purpose DRAM interfaces.
Solution Approach 2:
The holding circuit and refresh control circuit work together to provide universal functionality across different memory banks. Each bank can independently enter refresh mode based on its own data write status, making the system adaptable to various usage patterns while maintaining standard DRAM compatibility and reducing current consumption without requiring specialized external control sequences.
3Quantity of substance
If memory area is divided into multiple memory banks, then storage capacity is increased, but device complexity increases
Solution Approach 1:
The holding circuit and refresh control circuit are merged into an integrated unit for each memory bank. This combination reduces the overall device complexity by eliminating separate control logic while still enabling selective refresh functionality across multiple memory banks, thus maintaining increased storage capacity without proportionally increasing complexity.
Data Source
AI summary
A conventional semiconductor memory device may be in need of a special refresh sequence if it is desired to reduce the current consumption in connection with a refresh operation. With this in view, there is disclosed a semiconductor memory device 1 that has a recording area 30 formed by a plurality of memory banks 31 to 3n. The refreshing operation for this semiconductor memory device 1 may be performed on the memory bank basis. The semiconductor memory device 1 includes refresh control circuits 21 to 2n and holding circuits 11 to 1n in association individually with the memory banks 31 to 3n. The holding circuits 11 to 1n are set when data has been written in associated ones of the memory banks 31 to 3n following resetting of the semiconductor memory device. The refresh control circuits 21 to 2n set the associated memory banks 31 to 3n to a refresh enabling state in case the associated holding circuits 11 to 1n are in a set state (FIG. 1).