Selective Local Metal Cap Layer Formation for Electromigration
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Solution Overview
Problem
As integrated circuits are scaled to smaller dimensions, interconnects become increasingly susceptible to electromigration, leading to mechanical stress, delamination, and electrical shorts due to the mass transport of metallic atoms under unidirectional electrical current, which existing technologies struggle to mitigate effectively without compromising circuit performance.
Innovation Solution
The formation of selective local metal cap regions over copper lines within interlevel dielectric layers, with a conformal insulator layer, helps to act as diffusion barriers, reducing electromigration by lowering the rate of copper diffusion along the Cu/metal cap interface and preventing residual metal cap material between copper lines, thus enhancing current density tolerance without increasing interlevel vias or degrading circuit resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If interconnect linewidth is reduced to increase circuit density, then device density and performance are improved, but electromigration susceptibility increases leading to reliability degradation
Solution Approach 1:
The patent applies selective capping by depositing metal cap material only in specific regions where electromigration is most severe (e.g., near vias, bends, or high current density areas) rather than uniformly across all interconnects. This localized approach targets the harmful effects precisely where they occur most, improving reliability at critical points while maintaining the reduced linewidth design for overall density.
Solution Approach 2:
The patent employs composite interconnect structures combining copper interconnect lines with overlying metal cap layers (such as cobalt, tungsten, or other diffusion barrier materials). This composite structure leverages the low resistivity of copper for signal transmission while the cap layer provides electromigration protection and diffusion barrier functionality, creating a synergistic system that addresses both performance and reliability requirements.
2Reliability
If conventional electromigration mitigation techniques are applied, then reliability is improved, but circuit resistance increases or device complexity increases
Solution Approach 1:
The patent implements selective capping strategies where metal cap material is deposited only in regions requiring electromigration protection (such as near vias, bends, or high-stress areas) rather than applying caps uniformly across all interconnects. This localized approach reduces the overall material volume and process complexity compared to full-coverage capping, while still providing targeted reliability improvement where it is most needed.
Solution Approach 2:
The patent applies capping material to only the extent necessary for electromigration mitigation, using partial coverage strategies that deposit caps selectively at critical locations rather than providing excessive full-coverage protection. This partial action approach achieves sufficient reliability improvement without the added complexity and cost of complete interconnect capping.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces electromigration failures by acting as a diffusion barrier, increasing the allowed current density and preventing electromigration without significantly reducing conductor length or degrading circuit performance, while minimizing the risk of time-dependent dielectric breakdown.
Implementation Method 1
selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines
Implementation Method 2
forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines
Data Source
AI summary
A method of forming a wiring structure for an integrated circuit device includes forming one or more copper lines within an interlevel dielectric layer (ILD); masking selected regions of the one or more copper lines; selectively plating metal cap regions over exposed regions of the one or more copper lines; and forming a conformal insulator layer over the metal cap regions and uncapped regions of the one or more copper lines.