Selective Metal Cap Formation for Electromigration Suppression
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Solution Overview
Problem
As integrated circuits are scaled to smaller dimensions, interconnects become increasingly susceptible to electromigration, leading to mechanical stress, delamination, and electrical shorts due to the mass transport of metallic atoms under electrical current, which existing technologies struggle to mitigate effectively without compromising circuit performance.
Innovation Solution
The formation of selective local metal cap regions with a spacing corresponding to a critical length, where the back stress gradient balances electromigration forces, suppressing mass transport, and the use of staggered metal cap locations along a common longitudinal axis to enhance electromigration reliability and reduce resistance-capacitance (RC) concerns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect linewidth dimensions are reduced to increase density and performance, then device speed and circuit functionality are improved, but electromigration susceptibility increases leading to mass transport of metallic atoms
Solution Approach 1:
The patent applies local quality by forming metal cap regions at specific locations along the interconnect lines rather than uniformly across the entire interconnect structure. The cap regions are selectively positioned at intervals to provide localized electromigration protection where it is most needed, while leaving other regions uncapped to maintain low resistance and capacitance. This selective capping approach allows the interconnect to maintain high performance while providing targeted reliability improvement.
Solution Approach 2:
The patent segments the continuous interconnect line into multiple sections by introducing discrete metal cap regions at periodic intervals. Each cap region acts as an independent barrier to mass transport, creating segmented protection zones. The spacing between cap regions is optimized to be less than the critical length L, ensuring that electromigration forces are counteracted in each segment while maintaining overall circuit performance.
2Reliability
If metal cap regions are formed to suppress electromigration, then mass transport of electrons is reduced, but resistance and capacitance may increase
Solution Approach 1:
The patent applies partial action by forming metal cap regions only at specific intervals along the interconnect lines rather than covering the entire length. The cap regions are positioned at staggered locations on adjacent lines and spaced at distances less than the critical length L, providing sufficient electromigration protection while minimizing the total amount of cap material deposited. This partial capping approach reduces the impact on resistance and capacitance compared to full-coverage capping.
Solution Approach 2:
The patent optimizes the spacing parameter between metal cap regions to be less than the critical length L, which is the distance at which back stress gradient balances electromigration force. By controlling this spacing parameter, the patent achieves effective electromigration suppression while minimizing the number and size of cap regions required, thereby reducing the associated resistance and capacitance penalties.
3Reliability
If metal cap regions are formed at regular intervals to balance back stress gradient and electromigration force, then mass transport is suppressed, but device complexity increases
Solution Approach 1:
The patent introduces asymmetry by forming metal cap regions at staggered locations on adjacent interconnect lines rather than at identical positions. This asymmetric arrangement breaks the symmetry of the interconnect structure, which helps to reduce coupling effects and parasitic interactions between adjacent lines. The staggered positioning also simplifies the masking process, as it allows for more flexible mask design and alignment tolerances compared to requiring precise simultaneous patterning of all lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses electromigration and extends the lifetime of interconnects by acting as diffusion barriers, reducing the risk of electrical shorts and improving circuit reliability without significantly increasing resistance or capacitance, thus allowing higher current densities without the need for additional interlevel vias.
Implementation Method 1
selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons
Implementation Method 2
Electromigration is a term referring to the phenomenon of mass transport of metallic atoms (e.g., copper or aluminum) which make up the interconnect material, as a result of unidirectional or DC electrical current conduction therethrough
Data Source
AI summary
A method of forming a wiring structure for an integrated circuit device includes forming a first metal line within an interlevel dielectric (ILD) layer, and forming a second metal line in the ILD layer adjacent the first metal line; masking selected regions of the first and second metal lines; selectively plating metal cap regions over exposed regions of the first and second metal lines at periodic intervals such that a spacing between adjacent metal cap regions of an individual metal line corresponds to a critical length, L, at which a back stress gradient balances an electromigration force in the individual metal line, so as to suppress mass transport of electrons; and wherein the metal cap regions of the first metal line are formed at staggered locations with respect to the metal cap regions of the second metal line, along a common longitudinal axis.