Selective Metal Capping on Copper Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for fabricating integrated circuits with copper interconnects face challenges in preventing copper diffusion into low dielectric constant layers due to the aggressive nature of reaction ion etching processes, which can damage or thin the tantalum nitride barrier layers, leading to electrical shorting and ineffective diffusion barriers.
Innovation Solution
A metal capping layer, composed of cobalt (Co), ruthenium (Ru), tungsten (W), or manganese (Mn), is selectively deposited onto the sidewalls of copper lines, avoiding the need for aggressive etching processes by leaving exposed dielectric portions untouched, thereby forming a robust diffusion barrier that inhibits copper diffusion into the low dielectric constant layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If reaction ion etching is used to remove TaN barrier layer between copper lines, then electrical shorting is eliminated, but the TaN barrier layer is damaged or thinned, reducing its ability to prevent copper diffusion
Solution Approach 1:
The patent extracts and removes only the portions of the TaN barrier layer that are laterally adjacent to copper lines (between copper lines), while preserving the TaN barrier layer portions that overlie the copper lines and their sidewalls. This selective removal eliminates electrical shorting between copper lines while maintaining the diffusion barrier function where needed.
Solution Approach 2:
The patent applies different treatments to different regions of the TaN barrier layer: lateral portions between copper lines are removed to prevent shorting, while vertical portions overlying copper lines and sidewalls are retained to prevent copper diffusion. This local differentiation resolves the contradiction by optimizing each region for its specific function.
2Reliability
If uniform TaN barrier layer is deposited over copper lines and exposed dielectric, then copper diffusion is prevented, but aggressive etching damages the barrier layer and creates electrical shorting
Solution Approach 1:
The patent selectively removes (extracts) only the lateral portions of the uniform TaN barrier layer that are disposed between copper lines, while preserving the vertical portions that overlie the copper lines and sidewalls. This extraction eliminates electrical shorting pathways while maintaining copper diffusion prevention.
Solution Approach 2:
The patent creates local quality differentiation in the barrier layer structure by removing TaN laterally between copper lines (allowing electrical isolation) while retaining TaN vertically over copper lines and sidewalls (maintaining diffusion barrier). This resolves the contradiction between preventing shorting and preventing diffusion.
3Ease of operation
If RIE etching process is used to remove TaN barrier layer, then copper line isolation is achieved, but the etching process is too aggressive and damages remaining barrier layer portions
Solution Approach 1:
The patent uses RIE etching to extract and remove only the lateral portions of the TaN barrier layer between copper lines, where precision damage to the barrier is less critical. The process is controlled to stop before significantly damaging the vertical barrier portions that overlie copper lines and sidewalls.
Solution Approach 2:
The patent applies local quality control by allowing more aggressive etching in lateral regions between copper lines (where barrier removal is desired for isolation) while protecting vertical barrier regions over copper lines and sidewalls (where barrier integrity is critical for diffusion prevention).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents copper diffusion into the low dielectric constant layers, maintaining the integrity of the barrier and enhancing the reliability of the integrated circuits by avoiding damage from etching processes, thus ensuring improved electrical performance.
Implementation Method 1
selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed
Data Source
AI summary
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes selectively depositing a metal capping layer on first sidewalls of a copper line while leaving exposed portions of a dielectric layer that are laterally adjacent to the copper line exposed. An ILD layer is deposited overlying the metal capping layer and the exposed portions of the dielectric layer.