Selective Metal Gate GAA Structures for Threshold Voltage Uniformity
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is compounded by constraints on lithographic processes and trade-offs between feature dimension and spacing, leading to issues like non-uniform threshold voltage and resistance variations.
Innovation Solution
The implementation of selectively grown metal gate structures and dipole layers to tune threshold voltage, combined with gate-all-around architectures and backside reveal processing, addresses these challenges by eliminating non-uniformity and improving gate resistance, enabling robust and efficient fabrication of nanowire and nanoribbon transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to below 10 nanometer node, then increased density of functional units is achieved, but non-uniform threshold voltage and resistance variations occur
Solution Approach 1:
The patent applies local quality by using selective epitaxial growth to create different gate structures in different regions. Specifically, metal gates are selectively grown only in NMOS device regions while PMOS regions receive dielectric fills, achieving local differentiation to compensate for scaling-induced non-uniformities in threshold voltage and resistance across the chip.
Solution Approach 2:
The patent changes physical and chemical parameters through selective epitaxial growth conditions. By controlling deposition parameters such as temperature, pressure, and precursor flow rates, the process achieves uniform metal gate formation in targeted regions while maintaining different structures elsewhere, thereby resolving threshold voltage non-uniformity issues at scaled dimensions.
2Quantity of substance
If feature dimension is reduced to increase density, then spacing between features becomes constrained, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent segments the gate structure fabrication into distinct regions using selective epitaxial growth. By dividing the chip into NMOS regions (receiving metal gates) and PMOS regions (receiving dielectric fills), the process avoids the need for complex lithographic patterning at ultra-fine dimensions, thereby reducing lithographic process complexity while maintaining high functional unit density.
3Ease of manufacture
If conventional tri-gate fabrication process is used on bulk silicon substrates, then lower cost and simpler process are achieved, but mobility improvement and short channel control deteriorate at sub-10 nanometer dimensions
Solution Approach 1:
The patent applies local quality by implementing gate-all-around structures with selective metal gate growth specifically in regions where short channel control is critical. The selective epitaxial growth creates three-dimensional gate structures that fully surround the channel, providing superior electrostatic control compared to conventional planar or tri-gate structures, while maintaining compatibility with bulk silicon substrates.
4Manufacturing precision
If selective epitaxial growth is used to form metal gates, then non-uniform threshold voltage is eliminated, but process complexity increases
Solution Approach 1:
The patent employs self-service through self-aligned selective epitaxial growth. The process uses the existing device structure and spacer layers as natural masks, allowing metal gates to grow automatically in the correct locations without requiring additional lithographic steps or complex alignment procedures. This self-aligning mechanism achieves uniform threshold voltage while minimizing the increase in process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by eliminating non-uniform threshold voltage and resistance variations, facilitating improved mobility and short channel control, while reducing manufacturing costs and enabling wider interconnect pitches.
Implementation Method 1
A first conductive layer is formed over the first gate dielectric in a first region of the semiconductor substrate. A second conductive layer is formed over the second gate dielectric in a second region of the semiconductor substrate
Implementation Method 2
dipole layers to tune threshold voltage
Data Source
AI summary
Integrated circuit structures having selectively grown metal gate structures are described. For example, a structure includes a first vertical arrangement of horizontal nanowires or fin laterally spaced apart from a second vertical arrangement of horizontal nanowires or fin. A first gate stack is over the first vertical arrangement of horizontal nanowires or fin, the first gate stack having a first conductive layer over a first gate dielectric, and a first conductive fill over the first conductive layer. A second gate stack is over the second vertical arrangement of horizontal nanowires or fin, the second gate stack having a second conductive layer over a second gate dielectric, and a second conductive fill over the second conductive layer and over the first conductive fill. A portion of the second conductive fill is laterally adjacent to the first conductive fill without having the second conductive layer there between.