Selective Module Parsing for Logical Equivalence Check Load Time
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Solution Overview
Problem
Conventional logical equivalence tools face a tradeoff between load time and accuracy when checking for logical equivalence between circuit designs, as they typically load the entirety of each design, even when only a subset is of interest, and the generation of additional design files can be error-prone.
Innovation Solution
A system that selectively loads design data by identifying a hierarchy of modules, performing a depth-first search to parse only the necessary modules, and generating a data structure for logical equivalence checks, thereby reducing the load time and maintaining accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the logical equivalence tool loads the entirety of each design, then the accuracy of the logical equivalence check is maintained, but the load time increases significantly
Solution Approach 1:
The patent segments the design into a hierarchy of modules, allowing the tool to parse and load only specific modules rather than the entire design. This is achieved by identifying a root module and selectively parsing only the modules in the hierarchy that are relevant to the equivalence check, thereby reducing load time while maintaining accuracy for the checked portions.
Solution Approach 2:
The patent extracts only the necessary portions of the design data by identifying and parsing only the specific modules required for the equivalence check. The system determines which modules to parse based on the hierarchy structure and the specific equivalence check requirements, extracting only the essential data needed rather than loading the complete design.
2Loss of time
If the tool generates additional design files to reduce loading burden, then the load time decreases, but the accuracy may be compromised due to generation errors
Solution Approach 1:
The patent performs preliminary identification of the module hierarchy structure before parsing. By first identifying the root module and the hierarchy relationships, the system can then selectively parse only the necessary modules in a controlled manner, avoiding the need for error-prone generation of additional design files while ensuring accurate parsing of the required portions.
3Loss of time
If the tool parses only a subset of modules, then the load time is reduced, but the completeness of the design representation may be compromised
Solution Approach 1:
The patent implements a dynamic approach where the set of parsed modules is determined based on the specific equivalence check requirements and the module hierarchy. The system can adaptively select which modules to parse depending on the check scope, ensuring that the parsed modules collectively represent the necessary portions of the design for accurate equivalence verification without unnecessarily loading the entire design.
Data Source
AI summary
This application discloses a system implementing tools and mechanisms to selectively load design data for logical equivalency check. The tools and mechanisms can identify a hierarchy of modules in a circuit design, perform a depth-first search of the hierarchy of modules starting with a root module to identify a subset of modules to parse, and selectively parse the subset of the modules in the circuit design. The tools and mechanisms can utilize the parsed subset of the modules to determine logical equivalence of the circuit design with at least another circuit design.