Selective Multithreaded Memory Training for CPU Sockets

Solution Overview

Problem

The increasing complexity of memory training steps with newer memory standards leads to longer boot times in multi-socket computer systems, especially when memory reference code (MRC) is executed serially across CPU sockets, which can exceed power constraints and result in potential damage to servers.

Innovation Solution

Implementing a selective multithreading (SMT) approach that dynamically enables multithreading based on power constraints and memory configurations of CPU sockets, allowing parallel execution of memory training on a subset of sockets while prioritizing power management to minimize boot time without exceeding power limits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If memory training is executed serially across CPU sockets, then power consumption is reduced, but boot time increases significantly

Engineering Contradiction:

Improvepower consumptionVSAvoidboot time

Core Design Contradiction:

Use of energy by stationary objectVSLoss of time

Solution Approach 1:

The patent implements dynamic multithreading enablement where the system automatically adjusts the number of CPU sockets executing memory training in parallel based on real-time power availability. The bootstrap processor monitors power constraints and dynamically schedules memory training tasks across available sockets, transitioning between serial and parallel execution modes as needed, thereby optimizing both boot time and power consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the execution parameter from fixed serial execution to variable parallel execution by adjusting the number of active threads based on power constraints. The patent modifies the memory training execution model to allow flexible distribution of training tasks across different numbers of CPU sockets, transforming a static time-consuming process into a dynamic one that adapts to power availability.

Inventive Principle:

Principle #35Parameter changes

2Loss of time

If multithreading is enabled for parallel memory training execution, then boot time is reduced, but power consumption may exceed constraints

Engineering Contradiction:

Improveboot timeVSAvoidpower consumption

Core Design Contradiction:

Loss of timeVSUse of energy by stationary object

Solution Approach 1:

The bootstrap processor continuously monitors power consumption during memory training and uses this feedback to adjust the number of active multithreads. When power constraints are approached, the system reduces the number of simultaneously executing sockets; when power headroom is available, it increases parallel execution, creating a closed-loop control system that balances boot time reduction with power constraint compliance.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent implements dynamic multithreading enablement where the system automatically adjusts the number of CPU sockets executing memory training in parallel based on real-time power availability. The bootstrap processor monitors power constraints and dynamically schedules memory training tasks across available sockets, transitioning between serial and parallel execution modes as needed, thereby optimizing both boot time and power consumption.

Inventive Principle:

Principle #15Dynamics

3Loss of time

If all CPU sockets execute memory training in parallel, then boot time is minimized, but power constraints are exceeded causing potential damage

Engineering Contradiction:

Improveboot timeVSAvoidserver safety

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent applies partial action by enabling multithreading only to the extent necessary to reduce boot time without exceeding power constraints. Rather than always executing all sockets in parallel (excessive action), the system activates only the appropriate number of threads based on real-time power availability, ensuring safe operation while maximizing performance benefits.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The bootstrap processor continuously monitors power consumption during memory training and uses this feedback to adjust the number of active multithreads. When power constraints are approached, the system reduces the number of simultaneously executing sockets; when power headroom is available, it increases parallel execution, creating a closed-loop control system that balances boot time reduction with power constraint compliance.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20230039807A1Selective multithreaded execution of memory training by central processing unit(CPU) sockets

Publication Date: 2023.02.09 INTEL CORP

AI summary

Embodiments described herein are generally directed to selective multithreaded execution of memory training by CPU sockets. In an example, a memory configuration and a current phase of execution of memory training for each of multiple CPU sockets of a computer system is received. Based on the memory configuration and the current phase of execution of each of the CPU sockets an estimated power usage across all CPU sockets may be determined. Based on the estimated power usage and a power consumption threshold (e.g., PTAM or PA), performance of the current phase of execution of one or more CPU sockets may be selectively released for one or more channels of the one or more CPU sockets.