Selective Parasitic Extraction for Circuit Design
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Solution Overview
Problem
In electronic design automation, parasitic extraction tools face challenges with memory and processing resource consumption when dealing with smaller feature size designs, leading to increased noise and cross-talk between nets, which slows down the generation of parasitic electrical models and netlists.
Innovation Solution
The implementation of a sequenced extraction method that pre-processes the physical layout to determine net attributes, orders extraction based on location, and uses space filling curves to evaluate areas for net extraction, while selectively decoupling capacitive couplings to reduce memory consumption and improve processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parasitic extraction is performed on all nets in small feature size designs, then complete parasitic models are obtained, but memory consumption increases significantly
Solution Approach 1:
The patent segments the set of all nets into two categories: extraction candidate nets (selected based on geometric criteria such as proximity and orientation) and non-candidate nets (excluded from extraction). This segmentation allows the tool to focus computational and memory resources only on nets that are likely to have significant parasitic effects, thereby reducing memory consumption while maintaining model completeness for critical nets.
Solution Approach 2:
The patent applies different processing quality levels to different nets based on their local geometric characteristics. Extraction candidate nets, which exhibit specific geometric properties (such as parallel orientation and close proximity), undergo full parasitic extraction with high precision. Other nets receive simplified or no extraction, allocating resources locally where they are most needed rather than uniformly across all nets.
2Measurement precision
If parasitic extraction is performed on all nets, then accurate parasitic values are obtained, but processing time increases
Solution Approach 1:
The patent divides the parasitic extraction process into two phases: (1) identification of extraction candidate nets using geometric criteria, and (2) selective parasitic extraction only for candidate nets. This segmentation eliminates unnecessary extraction operations on nets that would not contribute significantly to model accuracy, thereby reducing processing time while preserving accuracy for critical nets.
Solution Approach 2:
Instead of performing full parasitic extraction on all nets (excessive action), the patent performs extraction only on a subset of nets that meet specific geometric criteria (partial action). This partial extraction approach is sufficient to capture the dominant parasitic effects in small feature size designs, achieving acceptable accuracy with significantly reduced processing time.
3Quantity of substance
If sequential net-by-net extraction is performed, then memory usage is managed, but processing efficiency decreases
Solution Approach 1:
The patent performs preliminary identification of extraction candidate nets using geometric criteria before the actual parasitic extraction process. This preliminary action creates a filtered list of candidate nets that can be processed efficiently in batches or parallel, rather than sequentially one-by-one. The preprocessing step enables more efficient subsequent extraction while maintaining controlled memory usage.
Data Source
AI summary
This application discloses a computing system to pre-process a physical or geometric layout of a circuit design to determine various attributes of the nets, such as a location and a total capacitance for each net in the geometric layout. The computing system can order extraction of the nets from the geometric layout of the circuit design with a space filling curve based, at least in part, on the locations of the nets in the geometric layout of the circuit design and any coupling capacitance between the nets in the geometric layout of the circuit design. The computing system can selectively decouple nets with a coupling capacitance based, at least in part, on the total capacitance for the nets associated with the coupling capacitance. The computing system can generate an electrical representation for each of the extracted nets and write them to a netlist for the circuit design.