Selective Ethernet Pause Frame for Buffer Overflow Control

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Solution Overview

Problem

Layer-2 Ethernet switches have limited buffer management and flow control, leading to buffer overflow issues when handling bursty traffic, causing unnecessary latency and packet drops, especially since traditional pause frames affect all connected ICs regardless of their traffic needs.

Innovation Solution

Implementing a custom pause frame mechanism that selectively addresses the source of traffic overload by using a unique type field and unicast addressing to pause only the offending IC, allowing other traffic to continue uninterrupted, and employing programmable ICs to monitor buffer levels and send tailored pause frames.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional pause frames are used to control traffic flow, then buffer overflow is prevented, but all connected ICs are paused regardless of their traffic needs, causing unnecessary latency

Engineering Contradiction:
Improvebuffer overflow preventionVSAvoidlatency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the flow control mechanism by introducing a type field in pause frames that allows differentiating between global pause requests (affecting all ports) and selective pause requests (affecting specific source ICs). This segmentation enables precise control where only the offending traffic source is paused while other ICs continue uninterrupted, thus preventing buffer overflow without imposing unnecessary latency on unrelated traffic flows.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by enabling pause frames to target specific source ICs rather than applying a uniform pause to all connected devices. The type field and source addressing mechanism allow the switch to apply flow control locally to only those ICs generating excessive traffic, ensuring that buffer overflow prevention is applied where needed while maintaining normal operation for other ICs, thereby avoiding unnecessary latency.

Inventive Principle:
Principle #3Local quality

2Device complexity

If simple layer-2 switching is used, then device complexity is reduced, but buffer management capability is insufficient, leading to packet drops under bursty traffic

Engineering Contradiction:
Improveswitch intelligenceVSAvoidbuffer management
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent changes the parameters of existing pause frame structure by adding a type field and enhancing source addressing capabilities. This parameter change allows simple layer-2 switches to achieve improved buffer management without requiring complex intelligence. The modified pause frame format enables the switch to identify and control specific traffic sources, providing effective buffer overflow prevention while maintaining the simplicity of layer-2 switching architecture.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If pause frames are sent to all ports to prevent overflow, then buffer protection is ensured, but traffic flow to non-offending ICs is interrupted

Engineering Contradiction:
Improvebuffer protectionVSAvoidtraffic flow continuity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the pause frame functionality to distinguish between global and selective pause operations. By introducing a type field that identifies whether a pause frame applies to all ports or a specific source IC, the system can protect buffers from overflow while maintaining continuous traffic flow to ICs that are not the source of the problem. This segmentation ensures that buffer protection is applied precisely where needed without disrupting overall network productivity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The type field acts as an intermediary mechanism that mediates between the need for buffer protection and the need to maintain continuous traffic flow. It enables the switch to interpret pause frame intent correctly and apply flow control only to the appropriate source ICs, thereby protecting buffers while allowing uninterrupted traffic to non-offending ICs and maintaining system-wide productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9608919B2Multi-level flow control
Publication Date: 2017.03.28 ARRIS ENTERPRISES LLC
  • US9608919B2 patent drawing
  • US9608919B2 patent drawing
  • US9608919B2 patent drawing

AI summary

Various methods, systems, and apparatuses can be used to control flow in an ethernet environment. In some implementations, methods can include receiving a flow of ethernet frames at a first device via an ethernet switch, determining that a buffer at the first device exceeds a threshold for an incoming flow, generating an initial pause frame operable to pause only a second device, and transmitting the initial pause frame to the ethernet switch.