Selective Plane Program Verification for Faster Memory Writes

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Solution Overview

Problem

Performing program verify operations in memory devices increases power consumption and write time, while skipping them leads to reliability risks due to potential storage of incorrect data, especially as memory cells degrade over time.

Innovation Solution

Implement a selective plane data program verification system that provides verification pulses to a proper subset of planes during programming, reducing the overall workload and allowing faster ramping times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If program verification is performed on all planes, then data reliability is improved, but power consumption and write time increase

Engineering Contradiction:

Improvedata reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The memory device is divided into multiple planes, and program verification is selectively applied to a proper subset of planes rather than all planes. This segmentation allows the system to verify data in only the necessary planes, reducing overall power consumption while maintaining reliability for the verified portion.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of performing complete program verification on all planes (excessive action), the system applies verification to only a proper subset of planes (partial action). This partial verification approach reduces power consumption and write time while still providing sufficient reliability assurance for the memory operations performed.

Inventive Principle:

Principle #16Partial or excessive action

2Reliability

If program verification is performed on all planes, then data reliability is improved, but write time increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidwrite time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The memory device is divided into multiple planes, and program verification is selectively applied to a proper subset of planes rather than all planes. This segmentation allows the system to verify data in only the necessary planes, reducing overall write time while maintaining reliability for the verified portion.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Instead of performing complete program verification on all planes (excessive action), the system applies verification to only a proper subset of planes (partial action). This partial verification approach reduces write time while still providing sufficient reliability assurance for the memory operations performed.

Inventive Principle:

Principle #16Partial or excessive action

3Use of energy by moving object

If program verification is skipped, then power consumption and write time are reduced, but reliability risks increase due to potential incorrect data storage

Engineering Contradiction:

Improvepower consumptionVSAvoiddata reliability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system implements program verification as a feedback mechanism that checks whether data was correctly written to memory cells. By applying verification to a proper subset of planes, the system obtains feedback on data integrity for those planes while avoiding the complete verification overhead that would consume excessive power and time.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20260051357A1Selective plane data program verification system

Publication Date: 2026.02.19 MICRON TECHNOLOGY INC

AI summary

A method for programming data in a memory device is described herein. The method includes providing a programming pulse via a controller to each of a plurality of word-lines in each of a plurality of sub-blocks of each of a plurality of planes of the memory device. The method further includes providing a verification pulse via the controller selectively to a set of the word-lines in one or more of the sub-blocks of a proper subset of the planes of the memory device.