Selective Prefetching of Physically Sequential Cache Lines
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Solution Overview
Problem
The latency associated with page table walks in microprocessors is high due to the finite size of the translation lookaside buffer (TLB), leading to costly operations when TLB misses occur, necessitating a reduction in the time required to perform these walks.
Innovation Solution
Incorporating hardware logic in microprocessors to determine if a physically sequential cache line is outside the page table and selectively prefetching it, thereby reducing the need for long latency reads from physical memory during TLB misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the translation lookaside buffer (TLB) size is increased to reduce TLB misses, then the time required for page table walks is reduced, but the device complexity and memory usage increase
Solution Approach 1:
The patent implements a prefetch mechanism that proactively loads page table entries into the TLB before they are actually needed. When a page table walk is initiated, the system prefetches the next sequential page table entries into the TLB, so that when they are needed, they are already available in the buffer, eliminating the need to wait for memory access. This preliminary action reduces the effective time for page table walks without permanently increasing TLB size.
Solution Approach 2:
The patent employs a dynamic prefetching strategy where the TLB is selectively updated with prefetched page table entries based on the current state of the page table walk. The system dynamically determines which entries to prefetch and when to insert them into the TLB, optimizing the balance between TLB utilization and memory bandwidth consumption without requiring a statically larger TLB.
2Loss of time
If page table entries are prefetched into the TLB, then the time for subsequent tablewalks is reduced, but the loss of information increases due to potential eviction of useful entries
Solution Approach 1:
The patent implements a lookahead mechanism that prefetches page table entries into a separate prefetch buffer before they are needed for actual translation. This preliminary loading allows the system to prepare future TLB entries without displacing currently valid translations, as the prefetch operations target a dedicated buffer rather than the main TLB structure.
Solution Approach 2:
The patent separates the TLB into functional segments: a main TLB for active translations and a prefetch buffer for upcoming entries. This segmentation allows prefetched entries to coexist with currently valid translations without causing evictions. The prefetch buffer acts as an intermediate storage that feeds the main TLB proactively, reducing conflicts between prefetching and active translation requirements.
3Productivity
If hardware logic is added to determine and selectively prefetch cache lines, then the productivity of page table walks is improved, but the device complexity increases
Solution Approach 1:
The patent incorporates hardware logic that automatically determines the physical addresses of next sequential page table entries and initiates prefetch operations without software intervention. This preliminary hardware-based address calculation and prefetch initiation occurs during the normal page table walk execution, overlapping the prefetch operation with the current translation task, thereby improving overall throughput without adding significant control complexity.
Solution Approach 2:
The prefetch mechanism is designed to be self-managing through hardware logic that automatically identifies when prefetching is needed, calculates the target addresses, and executes the prefetch operations. The system monitors its own state and autonomously initiates prefetching when conditions are favorable, reducing the need for complex external control logic while maintaining high productivity.
Data Source
AI summary
A microprocessor includes a translation lookaside buffer and a first request to load into the microprocessor a page table entry in response to a miss of a virtual address in the translation lookaside buffer. The requested page table entry is included in a page table. The page table encompasses a plurality of cache lines including a first cache line that includes the requested page table entry. The microprocessor also includes hardware logic that makes a determination whether a second cache line physically sequential to the first cache line is outside the page table, and a second request to prefetch the second cache line into the microprocessor. The second request is selectively generated based at least on the determination made by the hardware logic.