Selective Processor Core Wake-Up During Power Failure
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Solution Overview
Problem
Legacy systems experience significant power consumption and time delays due to waking all processor cores from a deep sleep state to an awake state during a power failure.
Innovation Solution
Implementing an interrupt control logic to manage core status transitions, ensuring only a subset of processor cores are moved to the awake state during power failure, based on a predefined threshold, thereby reducing unnecessary wake-ups and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all processor cores are woken from deep sleep state to awake state during power failure, then system reliability is improved, but power consumption increases significantly
Solution Approach 1:
The system segments the processor cores into different groups based on their wake-up requirements. Instead of waking all cores simultaneously, the patent implements selective wake-up where only essential cores are activated first, while non-essential cores remain in deep sleep state. This segmentation allows the system to maintain reliability for critical functions while reducing overall power consumption.
Solution Approach 2:
The patent applies partial action by waking up only the necessary subset of cores rather than all cores. The system determines the minimum number of cores required to handle power failure events and keeps only those cores in awake state, while leaving other cores in low-power state. This partial wake-up approach maintains sufficient system reliability while significantly reducing power consumption compared to waking all cores.
2Speed
If all processor cores are woken from deep sleep state to awake state during power failure, then system responsiveness is improved, but time consumption increases
Solution Approach 1:
The wake-up process is segmented into multiple phases. Essential cores are woken up first to handle critical power failure responses, while non-essential cores remain asleep. This phased approach allows the system to respond to power failures quickly using the minimal necessary processing power, avoiding the time penalty of bringing all cores online.
Solution Approach 2:
The system performs partial wake-up action by activating only the cores needed for power failure handling. By waking up a subset of cores rather than all cores, the system achieves sufficient responsiveness for power failure events while reducing the total time required for the wake-up process.
3Use of energy by moving object
If a subset of processor cores is kept in awake state during power failure, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The system performs preliminary classification of processor cores into essential and non-essential groups before power failure occurs. This pre-characterization is stored in system configuration, so when power failure happens, the system can immediately activate only the pre-identified essential cores without needing complex real-time decisions, thereby reducing operational complexity while maintaining power savings.
Solution Approach 2:
The patent introduces an intermediary power management controller that handles the complexity of selective core wake-up. This intermediary component manages the classification and activation logic, shielding the rest of the system from the complexity of selective core management while enabling power consumption reduction through intelligent core selection.
Data Source
AI summary
Embodiments herein relate to a power control unit (PCU) of an electronic device. The PCU may be configured to receive a power failure interrupt from an interrupt control block of the electronic device. The power failure interrupt may be generated based on or related to a power failure of the electronic device. In response to receipt of the power failure interrupt, and when a threshold number of processor cores related to the power failure is different than a number of awake processor cores of a set of processor cores of the electronic device, the PCU may transition a subset of processor cores of the set of processor cores to an awake state or a sleep state so that the number of awake processor cores is same as the threshold number of processor cores. Other embodiments may be described and/or claimed.