Selective Q-gating Flip-flop Grading for Scan-shift Power Control
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Solution Overview
Problem
The increasing logic density in integrated circuits leads to increased defects and challenges in controlling scan-shift power, particularly with Q-gating, which can result in higher active power consumption and power droop during testing.
Innovation Solution
A processor-implemented method for selective Q-gating of flip-flops in integrated circuit designs, determining maximum width, depth, and congestion values, and grading each flip-flop based on these parameters to identify critical nodes for Q-gating, thereby minimizing area-overhead and power droop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Q-gating is applied to control scan-shift power for the entire design, then power consumption during scan shifting is reduced, but active power to the design increases
Solution Approach 1:
The patent applies Q-gating selectively to specific flip-flops identified as critical based on grading criteria (width, depth, congestion) rather than uniformly to all flip-flops. This localized application reduces scan-shift power only where necessary while avoiding the penalty of increased active power across the entire design.
2Loss of energy
If Q-gating is applied to control scan-shift power, then power droop during testing is reduced, but area-overhead increases
Solution Approach 1:
The patent selectively applies Q-gating to critical flip-flops identified through grading based on width, depth, and congestion metrics. This selective approach reduces power droop only in critical areas while minimizing the overall area overhead compared to applying Q-gating universally across the entire design.
3Area of stationary object
If selective Q-gating is applied to critical nodes only, then area-overhead is minimized, but power droop control becomes less effective
Solution Approach 1:
The patent uses grading parameters (width, depth, congestion) to identify critical flip-flops that have the greatest impact on power droop. By targeting flip-flops with high grades in these parameters, the selective Q-gating approach maintains effective power droop control while minimizing area overhead compared to less targeted approaches.
Data Source
AI summary
A processor-implemented method for selective Q-gating flip-flops in a plurality of flip-flops contained in a design is provided. The method may include determining a maximum width, a maximum depth, and a maximum congestion value in the design and determining a relative width, a relative depth, and a relative congestion value for each of the plurality of flip-flops in the design. The method may further include determining grade values for each of the plurality of flip-flops in the design based on a ratio between the relative width, the relative depth and the relative congestion value, and the maximum width, the maximum depth, and the maximum congestion value, respectively and determining an overall summed value for each of the plurality of flip-flops. Then the method may sort the plurality of flip-flops based on the overall summed value for the plurality of flip-flops according to magnitude.