Selective RAID-5 Parity for Cache Memory Blocks

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Solution Overview

Problem

Data storage systems employing RAID schemes face challenges in efficiently managing cache memory, particularly in balancing memory space utilization and data recovery, as existing methods either store parity information for all cache blocks or fail to recover data without it, leading to potential losses during device failures.

Innovation Solution

A RAID data storage controller that differentiates between read and write cache blocks, storing read blocks without parity information to maximize memory space and computes parity only for write blocks, ensuring efficient data recovery by selectively using RAID-5 protection for write blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity information is stored for all cache blocks, then data recovery capability is improved, but memory space utilization deteriorates

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidmemory space utilization
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by differentiating between read cache blocks and write cache blocks, applying RAID protection selectively only to write cache blocks while storing read cache blocks without parity information. This localized approach to quality control optimizes memory space utilization while maintaining data recovery capability where it is most critical (for write blocks that may be lost before reaching the storage array).

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If memory space is maximized by not storing parity for read blocks, then memory space utilization is improved, but data recovery capability deteriorates

Engineering Contradiction:
Improvememory space utilizationVSAvoiddata recovery capability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements partial action by applying RAID protection only to write cache blocks rather than all cache blocks. This selective approach provides sufficient data recovery capability for the critical write blocks while avoiding the excessive storage overhead of protecting read blocks, thereby optimizing memory space utilization without compromising essential data recovery functionality.

Inventive Principle:
Principle #16Partial or excessive action

3Quantity of substance

If RAID protection is applied selectively only to write blocks, then memory space utilization is improved, but device complexity increases

Engineering Contradiction:
Improvememory space utilizationVSAvoidcontroller logic complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing cache blocks into two distinct categories: read cache blocks and write cache blocks. This segmentation enables the controller to apply different storage strategies to each category, with write blocks receiving RAID protection and read blocks stored without parity. The segmentation simplifies the overall system logic by creating clear, manageable categories rather than requiring complex selective protection decisions for each individual block.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9292228B2Selective raid protection for cache memory
Publication Date: 2016.03.22 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US9292228B2 patent drawing
  • US9292228B2 patent drawing
  • US9292228B2 patent drawing

AI summary

A RAID controller includes a cache memory in which write cache blocks (WCBs) are protected by a RAID-5 (striping plus parity) scheme while read cache blocks (RCBs) are not protected in such a manner. If a received cache block is an RCB, the RAID controller stores it in the cache memory without storing any corresponding parity information. When a sufficient number of WCBs to constitute a full stripe have been received but not yet stored in the cache memory, the RAID controller computes a corresponding parity block and stores the RCBs and parity block in the cache memory as a single stripe.