Selectively Raised Source/Drain Transistor Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The raised source/drain structure in semiconductor devices increases parasitic capacitance between the source/drain regions and the gate electrode, which is not effectively mitigated by existing technologies.
Innovation Solution
A semiconductor structure is developed where a lower raised source/drain region is formed on a planar source/drain region or semiconductor fin, with a contact-level dielectric material layer and a contact via hole extending to the lower raised source/drain region, and an upper raised source/drain region is formed only at the bottom portion of the contact via hole, preventing additional parasitic capacitance formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a raised source/drain structure is formed to reduce source and drain parasitic resistance, then the parasitic resistance is reduced, but the parasitic capacitance between the raised source/drain structure and the gate electrode increases
Solution Approach 1:
The patent applies local quality by forming the upper raised source/drain region only in specific locations where contact via holes are present, rather than uniformly across the entire source/drain region. This localized formation allows the structure to provide low resistance contact paths where needed while avoiding additional parasitic capacitance in areas where contact is not required. The selective spatial distribution of the raised region creates different electrical characteristics in different locations of the same source/drain structure.
2Reliability
If the raised source/drain structure is extended to reduce resistance further, then the resistance decreases, but the device complexity increases
Solution Approach 1:
The patent segments the raised source/drain structure into two distinct parts: a lower raised source/drain region formed on the planar source/drain region, and an upper raised source/drain region formed selectively at the bottom portion of contact via holes. This segmentation allows each part to serve a specific function - the lower region provides general resistance reduction while the upper region provides localized contact resistance reduction - without requiring a uniformly complex structure throughout the entire device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces parasitic capacitance by limiting the raised source/drain structure to the contacted areas, thereby enhancing device performance without increasing parasitic capacitance.
Implementation Method 1
a selective deposition process, which deposits a semiconductor material only on semiconductor surfaces and does not deposit any semiconductor material on a dielectric surface
Data Source
AI summary
A lower raised source/drain region is formed on a planar source/drain region of a planar field effect transistor or a surface of a portion of semiconductor fin adjoining a channel region of a fin field effect transistor. At least one contact-level dielectric material layer is formed and planarized, and a contact via hole extending to the lower raised source/drain region is formed in the at least one contact-level dielectric material layer. An upper raised source/drain region is formed on a top surface of the lower raised source/drain region. A metal semiconductor alloy portion and a contact via structure are formed within the contact via hole. Formation of the upper raised source/drain region is limited to a bottom portion of the contact via hole, thereby preventing formation of, and increase of parasitic capacitance by, any additional raised structure in source/drain regions that are not contacted.