Selective Data Receiver Amplification for Intersymbol Interference
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Solution Overview
Problem
Current data receiving circuits face challenges in accurately processing high-speed data signals due to intersymbol interference, and they consume excessive power while requiring improved signal adjustment capabilities.
Innovation Solution
A data receiving circuit is designed with a first amplification circuit that compares a data signal with two reference signals of different levels, and a second amplification circuit that selectively receives the signal pair with the larger level difference based on an enable signal and feedback signal, to reduce intersymbol interference and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a data receiving circuit processes high-speed data signals, then signal transmission rate is improved, but intersymbol interference increases and signal quality deteriorates
Solution Approach 1:
The patent divides the signal processing into multiple stages: a first amplification circuit performs initial amplification, a second amplification circuit performs selective amplification based on signal level detection, and a third amplification circuit performs final amplification. This segmented approach allows each stage to optimize for specific signal conditions, reducing intersymbol interference while maintaining high transmission rates
Solution Approach 2:
The second amplification circuit dynamically adjusts its operation based on the detected signal level. When the signal level indicates potential intersymbol interference, the circuit activates additional amplification paths. This dynamic adaptation allows the system to maintain high transmission rates while compensating for signal quality degradation in real-time
2Reliability
If an equalization circuit compensates for channel loss, then signal quality is improved, but power consumption increases
Solution Approach 1:
The second amplification circuit performs selective amplification based on signal level detection. Instead of continuously operating at full power, it activates additional amplification paths only when the signal level indicates potential intersymbol interference. This partial action approach maintains signal quality when needed while reducing power consumption during normal operation
Solution Approach 2:
The circuit periodically detects signal levels and adjusts amplification accordingly. The detection mechanism monitors signal characteristics and triggers selective amplification only during periods when intersymbol interference is detected, rather than maintaining constant high-power operation. This periodic adjustment optimizes the balance between signal quality and power consumption
3Reliability
If a data receiving circuit uses traditional equalization methods, then channel compensation is achieved, but receiving performance and accuracy need improvement
Solution Approach 1:
The patent applies different amplification strategies to different signal conditions. The first amplification circuit handles general signal amplification, while the second amplification circuit provides enhanced amplification specifically for signals showing signs of intersymbol interference. This localized quality adjustment improves accuracy for problematic signals without over-processing normal signals
Solution Approach 2:
The circuit incorporates feedback mechanisms where the output of the second amplification circuit is monitored and used to adjust subsequent processing. The feedback loop detects residual intersymbol interference and adjusts amplification parameters accordingly, continuously improving signal output accuracy while maintaining channel compensation
Data Source
AI summary
Provided is data receiving circuit, data receiving system and memory device. The data receiving circuit includes: first amplification circuit, configured to receive data signal, first reference signal and second reference signal, perform first comparison on the data signal and the first reference signal in response to sampling clock signal and output first signal pair, and perform second comparison on the data signal and the second reference signal and output second signal pair; second amplification circuit, configured to receive enable signal and feedback signal, selectively receive the first signal pair or the second signal pair as input signal pair based on the feedback signal during period in which the enable signal is at first level, receive the first signal pair during period in which the enable signal is at second level, amplify voltage difference of the first signal pair, and output first output signal and second output signal.