Selective Recess for Bonded Substrate Interconnect Reliability
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Solution Overview
Problem
In microelectronic packaging, the surfaces of dies or wafers must be extremely flat and clean for reliable direct bonding, but probing and processing can introduce surface variances and contaminants that weaken bonds, and reprocessing in clean room environments is costly and inconvenient.
Innovation Solution
Forming intentional recesses in the bonding surfaces of substrates to accommodate surface variances and contaminants, allowing for flush bonding and creating cavities that can be air-filled or filled with materials to ensure a reliable direct bond without additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If probing is performed on metallic pads prior to bonding, then electrical testing and validation are enabled, but surface topology variance increases due to pad material displacement
Solution Approach 1:
The patent performs probing operations on the metallic pads before the bonding process to enable electrical testing and validation. By conducting the probing action in advance, the system can identify and account for surface topology variances created by probe mark displacements before they affect the bonding quality, allowing for compensatory measures to be taken.
Solution Approach 2:
The patent modifies bonding parameters such as bonding pressure and temperature to accommodate surface topology variances caused by probe marks. By adjusting these parameters, the system can achieve reliable bonds even when surface displacement has occurred during probing, effectively compensating for the degraded surface precision.
2Reliability
If touch-up chemical-mechanical polishing is performed to smooth surface variances, then bond reliability improves, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent adjusts bonding parameters including increased bonding pressure and optimized temperature profiles to compensate for surface topology variances without requiring additional polishing steps. This parameter modification approach achieves reliable bonds while avoiding the added cost and complexity of touch-up chemical-mechanical polishing processes.
Solution Approach 2:
The patent accepts the surface displacement caused by probing as an inevitable byproduct and converts this potential harm into a manageable condition by using the displacement information to adjust bonding parameters. Rather than attempting to eliminate the probe marks through additional polishing, the system leverages knowledge of their location and magnitude to optimize bonding conditions, thereby achieving reliable bonds without additional manufacturing steps.
3Ease of manufacture
If dies are processed outside extreme clean room environments, then manufacturing flexibility and cost decrease, but surface contamination increases
Solution Approach 1:
The patent performs critical operations such as probing and bonding preparation in advance, before the dies are exposed to less controlled environments. By completing sensitivity-critical operations while the dies are still in clean room conditions, the system secures surface quality without requiring continuous clean room processing, thereby enabling manufacturing flexibility and cost reduction.
Solution Approach 2:
The patent acknowledges that surface contamination from processing outside clean rooms is inevitable but converts this challenge into an opportunity by using contamination detection and compensation techniques. The system identifies contaminated areas and adjusts bonding parameters or applies localized cleaning to achieve reliable bonds, thereby enabling flexible manufacturing without strict clean room requirements while maintaining bond quality.
Data Source
AI summary
Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.