Selective Reference Voltage Calibration in Memory Subsystems

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Solution Overview

Problem

Memory subsystems face inefficiencies during performance state transitions due to the time-consuming nature of full reference voltage calibrations, which can lead to increased downtime and reduced availability for handling requests from external agents.

Innovation Solution

Implementing a dynamic reference voltage calibration method that allows transitions through an intermediate performance state without performing a calibration in that state, using a previously calibrated reference voltage and terminating adjustments when the eye pattern narrows, thereby reducing the number of calibrations required.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full reference voltage calibration is performed during every performance state transition, then the reliability of signal sampling is improved, but the loss of time and system availability deteriorates

Engineering Contradiction:
Improvesignal sampling accuracyVSAvoidcalibration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by performing reference voltage calibration only when necessary (during initial system operation, periodic intervals, or when transitioning to performance states that require it) rather than during every performance state transition. This selective calibration approach maintains signal sampling accuracy while reducing unnecessary calibration time and system unavailability.

Inventive Principle:
Principle #16Partial or excessive action

2Manufacturing precision

If reference voltage calibration is performed at every performance state, then the manufacturing precision of signal levels is improved, but the productivity of the memory subsystem deteriorates

Engineering Contradiction:
Improvereference voltage accuracyVSAvoidsystem availability
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements partial action by calibrating reference voltage only at selected performance states (e.g., initial state and periodically thereafter) rather than at every state transition. This maintains adequate reference voltage accuracy for reliable operation while minimizing the impact on system productivity and availability.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the operational parameter from 'calibrate at every state' to 'calibrate selectively based on state characteristics'. The system determines whether calibration is necessary based on the target performance state requirements, allowing it to skip calibration for states that do not require it, thereby maintaining precision where needed while improving overall productivity.

Inventive Principle:
Principle #35Parameter changes

3Loss of time

If dynamic reference voltage calibration is implemented to reduce calibrations, then the loss of time is improved, but the reliability of signal sampling may deteriorate

Engineering Contradiction:
Improvetransition timeVSAvoidsignal sampling accuracy
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent dynamically changes the calibration parameter based on system conditions and performance state requirements. It uses criteria such as whether the target performance state requires calibration, current calibration status, and system operational context to determine whether to perform calibration. This ensures signal sampling reliability is maintained when necessary while minimizing unnecessary calibrations that would increase transition time.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11501820B2Selective reference voltage calibration in memory subsystem
Publication Date: 2022.11.15 APPLE INC
  • US11501820B2 patent drawing
  • US11501820B2 patent drawing
  • US11501820B2 patent drawing

AI summary

A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.