Selective Reseeding for Scan Test Compression

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Solution Overview

Problem

Current scan testing methods for integrated circuits (ICs) face inefficiencies due to high test data volume and application time, especially with increasing complexity and shrinking process technologies, leading to insufficient cost control and reduced fault coverage.

Innovation Solution

A scan test system utilizing a dual-PRPG architecture with compressor and decompressor structures (CODECs) and an instruction decode unit (IDU) for selective reseeding, which enables efficient data compression and decompression, reducing test pattern volume and application time while maintaining high fault coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If deterministic ATPG is used to generate test patterns, then fault coverage is improved, but storage area in tester and test application time increase significantly

Engineering Contradiction:
Improvefault coverageVSAvoidtest data volume
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the large set of deterministic ATPG test patterns into multiple smaller subsequences, each generated by a separate PRPG instance. This segmentation allows the tester to store and apply much smaller data sets while maintaining comprehensive fault coverage through coordinated operation of multiple PRPGs.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces on-chip compression structures (scan compressors and response compressors) as intermediaries between the tester and the DUT. These structures compress the test data before it enters the scan chains and compress the test responses before they leave the DUT, significantly reducing the data volume that must be stored and transferred by the tester.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If on-chip compression structures are added to reduce test data volume, then tester storage requirements are reduced, but device complexity increases

Engineering Contradiction:
Improvetest data volumeVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent designs the on-chip compression structures to serve multiple functions: scan chain loading, test pattern generation, and test response collection. The same PRPG instances and compression structures are used for both loading test patterns into scan chains and for collecting and compressing test responses, eliminating the need for separate dedicated structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the scan chain load function with the PRPG pattern generation function by directly connecting PRPG outputs to scan chain inputs through compression structures. This merging eliminates the need for separate test pattern storage and loading mechanisms, reducing overall device complexity while maintaining compression benefits.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple PRPG instances are used to generate test patterns for different scan chain groups, then test application time is reduced, but device complexity increases

Engineering Contradiction:
Improvetest application speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the scan chains into multiple groups, each served by a dedicated PRPG instance. This allows parallel generation and application of test patterns to different scan chain groups simultaneously, significantly reducing total test application time while keeping each PRPG instance relatively simple.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension of parallelism by operating multiple PRPG instances simultaneously on different scan chain groups. This multi-dimensional approach to test pattern generation allows concurrent operation rather than sequential processing, improving productivity without requiring each individual PRPG to be overly complex.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS9157961B2Two-level compression through selective reseeding
Publication Date: 2015.10.13 SYNOPSYS INC
  • US9157961B2 patent drawing
  • US9157961B2 patent drawing
  • US9157961B2 patent drawing

AI summary

A scan test system and technique compresses CARE bits and X-control input data into PRPG seeds, thereby providing a first compression. The scan test system includes a plurality of compressor and decompressor structures (CODECs). Each block of the design includes at least one CODEC. An instruction decode unit (IDU) receives scan inputs and determines whether a seed extracted from the scan inputs is broadcast loaded in the CODECs, multicast loaded in a subset of the CODECs, or individual loaded in a single CODEC. This sharing of seeds, exploits the hierarchical nature of large designs with many PRPGs, provides a second compression. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage, diagnosability, and performance.