Selective Routing of Local Memory Accesses in Data Processors
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Solution Overview
Problem
Data processor cores face increased hardware overhead and delays due to specialized instructions like atomic and decorated instructions, which require specialized handling, leading to inefficiencies in memory access and potential lockups.
Innovation Solution
A data processing system that selectively routes local access requests internally and external access requests through a system interconnect and memory controller, allowing external resources to handle specialized requests, reducing the need for additional hardware overhead within the data processor core.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If specialized handling for atomic and decorated instructions is implemented at the data processor core, then the primary read and write functions are correctly implemented, but hardware overhead increases and bus locking delays occur
Solution Approach 1:
The patent extracts the specialized instruction handling logic from the data processor core and relocates it to external memory controller resources. The load/store unit determines whether an access is specialized and routes it externally, removing the need for complex specialized handling circuitry within the core itself while maintaining correct implementation of atomic and decorated instructions
Solution Approach 2:
The patent introduces a routing mechanism in the load/store unit that acts as an intermediary between the data processor core and external resources. This intermediary determines whether access requests are specialized and directs them to external memory controller resources for handling, preventing bus locking delays while maintaining correct instruction execution
2Reliability
If specialized handling for atomic and decorated instructions is implemented at the data processor core, then the primary read and write functions are correctly implemented, but bus locking delays affect subsequent memory accesses
Solution Approach 1:
The patent extracts the specialized instruction handling from the core execution path and moves it to external resources. By routing specialized access requests outside the core, the time-consuming specialized handling operations no longer block the bus for subsequent accesses, eliminating the delay problem while maintaining correct execution
Solution Approach 2:
The patent segments the memory access path into local and external routes. Specialized instructions are routed through the external path while normal instructions use the local path, allowing parallel processing and preventing specialized operations from blocking subsequent memory accesses
3Adaptability or versatility
If additional hardware overhead is added to the data processor core to implement specialized handling, then specialized instructions can be executed, but the size of the data processor core increases
Solution Approach 1:
The patent extracts specialized handling capabilities from the data processor core and places them in external memory controller resources. The core maintains only the routing logic to identify and direct specialized requests, significantly reducing the core size increase while preserving full adaptability to execute atomic and decorated instructions
Solution Approach 2:
The patent makes external memory controller resources universal by enabling them to handle both normal memory accesses and specialized instruction handling. This multi-functionality eliminates the need for dedicated specialized handling circuitry in the core, maintaining versatility while minimizing core complexity
Data Source
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AI summary
A data processor (101) is disclosed that accesses its local memory (117) by routing requests through a data path (131, 103, 107, 132) that is external the data processor (101). A reservation/decoration controller (107) implements specialized handling associated with a received request to access local memory (117). In addition to implementing special handling, a memory controller (105) that is associated with the reservation/decoration controller (107) routes (132) a corresponding access request back to the data processor core to access its local memory (117).