Selective SAC Capping on FinFET Gates for Local Interconnect Isolation
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Solution Overview
Problem
In FinFETs, the self-aligned contact (SAC) capping layer complicates the formation of electrical connections between gates and local interconnects due to material differences, leading to difficulties in etching and poor connections, which increases manufacturing costs and reduces chip yield.
Innovation Solution
The selective capping method involves applying a dielectric capping layer only on gates that need electrical isolation from local interconnects, allowing for direct electrical connections to be formed without removing the SAC cap, by masking and etching specific gates and applying a capping layer only where necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an SAC cap is formed on all gates to provide electrical isolation, then electrical isolation between local interconnects and gates is improved, but the complexity of forming electrical connections to gates deteriorates
Solution Approach 1:
The patent applies selective SAC capping where only specific gates receive the dielectric capping layer based on their electrical connection requirements. Gates that need isolation get capped, while gates needing connections remain uncapped. This local differentiation resolves the contradiction by providing isolation only where needed, eliminating unnecessary complexity in connection formation for other gates.
2Reliability
If a dielectric capping layer is applied on gates requiring isolation, then electrical isolation is improved, but the manufacturing process complexity deteriorates
Solution Approach 1:
The patent uses a preliminary masking step before applying the dielectric capping layer to selectively protect only those gates that require electrical connections. This preliminary action enables subsequent blanket deposition of the capping layer to automatically result in selective capping, simplifying the manufacturing process while maintaining reliable electrical isolation where needed.
3Reliability
If SAC cap removal is performed to form electrical connections, then electrical connection formation is improved, but manufacturing precision deteriorates
Solution Approach 1:
Instead of removing the SAC cap to form connections, the patent inverts the approach by selectively preventing cap formation on gates that need connections. This inversion eliminates the need for post-deposition removal operations, thereby maintaining manufacturing precision while still achieving reliable electrical connections through the local absence of the capping layer.
Data Source
AI summary
FinFET structures and methods of forming such structures. The FinFET structures including a substrate; at least two gates disposed on the substrate; a plurality of source/drain regions within the substrate adjacent to each of the gates; a dielectric disposed between each gate and the plurality of source/drain regions adjacent to each gate; a dielectric capping layer disposed on a first one of the at least two gates, wherein no dielectric capping layer is disposed on a second one of the at least two gates; and a local interconnect electrically connected to the second one of the at least two gates, wherein the dielectric capping layer disposed on the first one of the at least two gates prevents an electrical connection between the local interconnect and the first one of the at least two gates.