Selective SAM Deposition on Tungsten Vias for Lower Resistance
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Solution Overview
Problem
As IC sizes decrease, reducing via resistance in semiconductor structures becomes critical for improved performance, and existing methods struggle to effectively minimize cladding and resistivity of via materials.
Innovation Solution
A method involving the formation of a self-assembled monolayer (SAM) using phenanthroline or its derivatives is applied to selectively deposit materials on metallic and non-metallic surfaces, allowing for the formation of a protected metallic surface and subsequent selective deposition of a liner on non-metallic surfaces, using atomic layer deposition techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a planar process is used to align and connect metallization layers, then the manufacturing process is simple, but via resistance cannot be effectively reduced
Solution Approach 1:
A self-assembled monolayer (SAM) is formed on the metallic surface before the deposition process. This preliminary action modifies the surface properties of the via, enabling selective deposition of via fill material while minimizing cladding on the via sidewalls, thereby reducing via resistance without complicating the manufacturing process
Solution Approach 2:
The self-assembled monolayer acts as an intermediary between the metallic via surface and the via fill material. This intermediary layer enables selective deposition by facilitating material deposition only where needed (at the via bottom) while preventing unwanted deposition on via sidewalls, thus reducing via resistance
2Length of moving object
If the spacing between metal lines is decreased, then IC size is reduced, but via resistance becomes more critical for performance
Solution Approach 1:
The SAM is formed in advance on the via surface before material deposition. This preliminary surface modification ensures that even as IC size and via spacing decrease, the via fill material deposits selectively at the via bottom with minimal sidewall cladding, maintaining low via resistance despite smaller feature sizes
Solution Approach 2:
The surface properties of the via are changed by forming a self-assembled monolayer, which alters the deposition behavior of subsequent materials. This parameter change (surface chemistry/properties) enables selective deposition that maintains low via resistance even as physical dimensions are reduced
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces via resistance by selectively forming a self-assembled monolayer on metallic surfaces, enhancing the conductivity of semiconductor structures while maintaining the integrity of non-metallic surfaces, thereby improving the performance of electronic devices.
Implementation Method 1
exposing a substrate with an exposed metallic surface to a first precursor comprising phenanthroline or a phenanthroline derivative
Implementation Method 2
exposing a substrate having an exposed metallic surface and an exposed non-metallic surface to a first precursor comprising phenanthroline or a phenanthroline derivative to form a protected metallic surface
Implementation Method 3
A material is selectively deposited on the exposed non-metallic surface over the protected metallic surface
Data Source
AI summary
Methods for selectively depositing a self-assembled monolayer (SAM) on metallic surfaces are disclosed. Some embodiments of the disclosure utilize phenanthroline or a phenanthroline derivative to form the self-assembled monolayer. Some embodiments selective form the self-assembled monolayer on tungsten or molybdenum. Some embodiments utilize the self-assembled monolayer to selectively deposit on dielectric surfaces over metallic surfaces.