Selective Scan Insertion for Rapid IC Verification
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Solution Overview
Problem
The verification process for integrated circuits is delayed due to the need to wait until a register-transfer level (RTL) description is synthesized, causing production delays and increased costs, as multiple design teams are involved in identifying and remedying issues, and thorough verification is required post-remediation.
Innovation Solution
Implementing a selective scan insertion system that allows for early verification by selectively inserting and testing scan chains at specific circuit nodes, using a test harness to simulate and verify circuit operation, reducing the need for full circuit synthesis and enabling faster troubleshooting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full circuit synthesis is performed before verification, then verification completeness is improved, but verification time and production cycle are significantly increased
Solution Approach 1:
The patent divides the verification process into two stages: selective scan verification performed early on RTL descriptions, and comprehensive verification performed later on synthesized designs. This segmentation allows early detection of major issues without requiring complete synthesis, thereby reducing verification time while maintaining verification quality through the two-stage approach.
Solution Approach 2:
The patent performs preliminary verification actions by inserting scan chains selectively at the RTL description stage, before full synthesis is completed. This preliminary verification catches design errors early in the development cycle, preventing wasted time on synthesizing designs that contain fundamental flaws, thus resolving the time-completeness contradiction.
2Productivity
If scan chains are inserted early in the design process, then verification speed is improved, but design complexity and resource requirements are increased
Solution Approach 1:
The patent applies scan chains selectively at specific locations within the circuit design rather than uniformly across the entire design. By identifying critical paths and key functional blocks that benefit most from scan verification, the method achieves high verification productivity while minimizing the added design complexity to only those necessary locations.
Solution Approach 2:
The patent performs partial scan insertion rather than complete scan chain insertion across the entire design. This partial action provides sufficient verification capability to achieve high productivity in detecting major design errors, while avoiding the excessive complexity that would result from inserting scan chains throughout the entire circuit.
3Reliability
If multiple design teams are involved in verification, then verification thoroughness is improved, but communication overhead and cost are increased
Solution Approach 1:
The patent enables early verification teams to perform thorough checks on RTL descriptions with selective scan insertion before synthesis. This preliminary thorough verification by a single team or smaller group catches issues early, reducing the need for extensive coordination between multiple teams later in the process, thereby maintaining verification thoroughness while reducing process complexity.
Data Source
AI summary
Techniques for implementing selective scan insertion and verification that reduce production and verification time by enabling a test harness to insert and test scan chains are disclosed. Circuit nodes in a system model are selected and scan insertion is provided at the selected nodes. Selective scan insertion can be performed quickly and, in some implementations, automatedly to enable verification of correspondence of different system models or one or more system models and fabricated circuits. A request for manufacture may be generated including aspects of the system model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the system model.