Selective Segment Via Plating for PCB Signal Integrity
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Solution Overview
Problem
Conventional printed circuit board (PCB) manufacturing processes, such as sequential lamination and back drilling, face challenges in accurately aligning vias and controlling the length of via stubs, leading to performance issues and increased costs.
Innovation Solution
The selective segment via plating process involves applying plating resist to a conductive layer of an inner core, followed by electroless and electroplating processes to create a via wall plating discontinuity, allowing for separate segment connections within a single lamination step, eliminating the need for back drilling and improving alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sequential lamination is used to form separate via segments, then via alignment precision deteriorates, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the via plating into multiple discrete segments along the via wall. Plating resist is applied at specific locations to block plating deposition in certain regions, creating electrically isolated segments within the via. This allows precise control over which conductive layers are interconnected while maintaining a single lamination structure, thereby improving via alignment precision without increasing manufacturing process complexity.
Solution Approach 2:
The patent uses plating resist as an intermediary material to control the plating process. The plating resist is applied to specific regions of the via wall to prevent plating deposition in those areas, creating the desired segment isolation. This intermediary approach enables precise segment control within a single lamination step, improving alignment precision while avoiding the complexity of sequential lamination processes.
2Reliability
If back drilling is performed to remove via stubs, then signal quality improves, but manufacturing cost and time increase
Solution Approach 1:
The patent applies preliminary action by pre-defining via segments during the lamination and plating process, rather than performing corrective actions like back drilling after via formation. By using plating resist to block plating in specific regions before the plating process completes, the via stubs are prevented from forming in the first place. This eliminates the need for subsequent back drilling operations, maintaining signal quality while significantly reducing manufacturing time and cost.
Solution Approach 2:
The patent converts the potential harm of via stubs into a benefit by using plating resist to strategically block plating deposition. Instead of allowing unwanted plating to form and then removing it (back drilling), the plating resist prevents harmful plating stubs from forming in the first place. This approach maintains signal quality by eliminating stubs while avoiding the time-consuming back drilling process.
3Manufacturing precision
If plating resist is applied to control via segments, then segment isolation precision improves, but process steps increase
Solution Approach 1:
The patent merges multiple functions into a single integrated process step. The plating resist application is combined with the lamination process, allowing segment isolation to be established during the primary manufacturing operation rather than as a separate subsequent step. This integration maintains high segment isolation precision while minimizing the increase in overall process complexity by consolidating operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables precise control over segment connections, reduces signal reflection and degradation, and minimizes the formation of plating stubs, while simplifying the manufacturing process and reducing costs by eliminating the need for sequential lamination and back drilling.
Implementation Method 1
followed by electroless and electroplating processes to create a via wall plating discontinuity
Implementation Method 2
followed by electroless and electroplating processes to create a via wall plating discontinuity
Data Source
AI summary
A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.


