Selective Semiconductor Package Inspection System

Solution Overview

Problem

The semiconductor industry faces challenges with reduced yield due to the wafer level bonding-based semiconductor package, where all semiconductor chips in a package are typically tested, leading to increased manufacturing costs and decreased efficiency when any chip fails the package test.

Innovation Solution

An inspection system and method that selectively performs a package test process on semiconductor chips identified as good based on their identification information, allowing chips identified as bad to be skipped, thereby reducing unnecessary testing and increasing yield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If all semiconductor chips in a package are tested using conventional package test processes, then testing reliability is ensured, but manufacturing cost increases and productivity decreases due to unnecessary testing of bad chips

Engineering Contradiction:

Improvetesting reliabilityVSAvoidmanufacturing efficiency

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary identification of good and bad chips using identification information (such as EDS test results) before conducting package test processes. This preliminary sorting allows the inspection apparatus to selectively test only good chips, avoiding unnecessary testing of bad chips while ensuring testing reliability for packages that contain at least one good chip.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inspection apparatus automatically acquires identification information from the computer and uses it to autonomously determine which chips require testing. The system self-manages the selection process by comparing identification information against package composition data, eliminating the need for manual chip-by-chip inspection decisions.

Inventive Principle:

Principle #25Self-service

2Reliability

If all semiconductor chips in a package are tested, then quality assurance is maintained, but manufacturing cost increases due to wasted testing resources on bad chips

Engineering Contradiction:

Improvequality assuranceVSAvoidmanufacturing cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The system performs preliminary identification of good and bad chips using identification information (such as EDS test results) before conducting package test processes. This preliminary sorting allows the inspection apparatus to selectively test only good chips, avoiding unnecessary testing of bad chips while ensuring testing reliability for packages that contain at least one good chip.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

Instead of testing all chips in a package, the system performs partial testing only on chips identified as good. This partial action approach is sufficient to ensure package quality since a package with at least one good chip can function adequately, thereby reducing manufacturing costs without compromising quality assurance.

Inventive Principle:

Principle #16Partial or excessive action

3Manufacturing precision

If conventional package test processes are used on all chips, then comprehensive quality checking is performed, but processing time increases and productivity decreases

Engineering Contradiction:

Improvequality checking completenessVSAvoidprocessing time

Core Design Contradiction:

Manufacturing precisionVSLoss of time

Solution Approach 1:

The system performs preliminary identification of good and bad chips using identification information (such as EDS test results) before conducting package test processes. This preliminary sorting allows the inspection apparatus to selectively test only good chips, avoiding unnecessary testing of bad chips while ensuring testing reliability for packages that contain at least one good chip.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The inspection apparatus skips the package test process for chips identified as bad by acquiring identification information from the computer and using it to selectively determine which chips require testing. This skipping mechanism significantly reduces processing time while maintaining quality checking completeness for packages containing good chips.

Inventive Principle:

Principle #21Skipping (Rushing through)

Data Source

PatentUS11257723B2Inspection system and method for inspecting semiconductor package, and method of fabricating semiconductor package

Publication Date: 2022.02.22 SAMSUNG ELECTRONICS CO LTD

AI summary

An inspection system for a semiconductor package includes an inspection apparatus that includes a stage on which the semiconductor package is loaded, and a computer coupled to the inspection apparatus. The semiconductor package may include a first semiconductor chip and a second semiconductor chip on the first semiconductor chip, the computer may provide first identification information about the first semiconductor chip and second identification information about the second semiconductor chip, and the computer may control the inspection apparatus to selectively perform a package test process on one of the first and second semiconductor chips, the one of the first and second semiconductor chips being identified as a good chip based on the first identification information and the second identification information.