Selective Si Epitaxy With Halide Precursors for Low-Temperature Growth
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Solution Overview
Problem
The semiconductor industry faces challenges in forming epitaxial layers at lower temperatures to enable integration schemes such as monolithic integration, buried power rails, and high-k/metal gate first integration, particularly in achieving higher dopant concentration and reduced contact resistivity for improved source/drain formations in new device architectures like FinFET and GAA transistors.
Innovation Solution
A method and apparatus for forming a Si-comprising epitaxial layer selectively on a substrate using a silicon halide precursor containing iodine or bromine, allowing for epitaxial growth at lower temperatures while maintaining a higher growth rate and active dopant concentration, and enabling selective epitaxial growth on substrates with different surface orientations, along with a substrate processing apparatus that includes a process chamber, silicon precursor storage, and a controller for executing instructions to form the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional epitaxial growth methods are used, then higher temperatures are required for layer formation, but this consumes more temperature budget and limits integration scheme options
Solution Approach 1:
The patent changes the chemical parameters of the precursor material from conventional sources to silicon halide precursors containing iodine or bromine. This parameter change enables the epitaxial growth process to proceed at lower temperatures (reducing temperature budget consumption) while maintaining effective layer formation, thereby improving integration scheme flexibility without sacrificing productivity
2Temperature
If lower temperature epitaxial growth is attempted, then temperature budget is reduced, but growth rate typically decreases
Solution Approach 1:
The patent employs silicon halide precursors with iodine or bromine, which have different thermal and reactive properties compared to conventional precursors. This parameter change enables the decomposition and reaction to proceed efficiently at lower temperatures while maintaining high growth rates, breaking the typical inverse relationship between temperature and growth rate
3Manufacturing precision
If selective epitaxial growth is achieved through conventional means, then selectivity may be limited, but process complexity increases
Solution Approach 1:
The patent utilizes the unique chemical reactivity of silicon halide precursors containing iodine or bromine with specific crystal orientations. This parameter change in precursor chemistry enables highly selective epitaxial growth on certain crystal planes without requiring complex process sequences, achieving high manufacturing precision while keeping process complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of epitaxial layers with reduced resistivity and higher dopant concentration, improving source/drain contact performance and enabling the integration of new device architectures like GAA devices and buried power rails, while maintaining a lower temperature budget and enhancing semiconductor processing throughput.
Implementation Method 1
providing, to the process chamber, a Si-containing precursor, thereby forming a Si-comprising epitaxial layer on the exposed surface
Implementation Method 2
providing an etching gas to the process chamber, thereby removing, selectively, the first portion or the second portion of the epitaxial layer
Data Source
AI summary
A method for forming a Si-comprising epitaxial layer selectively on a substrate is disclosed. Embodiments of the presently described method comprise performing a cyclic deposition and etch processes, thereby forming selectively the Si-comprising epitaxial layer. The described method may help to form source/drain regions of field effect transistors in a bottom-up manner.