Selective SiGe Burial for pMOSFET Hole Mobility
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Solution Overview
Problem
The challenge lies in manufacturing semiconductor devices where SiGe burial in source and drain regions of pMOSFETs and nMOSFETs results in conflicting performance enhancements and degradations, making it difficult to achieve high-density gate electrode disposition without compromising either type of MOSFET performance.
Innovation Solution
A method involving the formation of cap films and selective etching to create concave portions in the semiconductor substrate, allowing for the embedding of semiconductor material SiGe, which applies compressive stress to the channel region of pMOSFETs while avoiding nMOSFETs, thereby optimizing mobility for both types of transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe is buried in source and drain region of pMOSFET to improve hole mobility, then hole mobility is enhanced, but SiGe must be selectively avoided in nMOSFET source and drain region which complicates the manufacturing process
Solution Approach 1:
The active region is divided into first active region (for pMOSFET) and second active region (for nMOSFET), allowing selective SiGe burial in only the first active region. This segmentation enables independent processing of pMOSFET and nMOSFET regions, resolving the contradiction between improving hole mobility through SiGe burial and avoiding degradation of nMOSFET performance.
Solution Approach 2:
SiGe is buried only in the source and drain regions of the first active region (pMOSFET) while the second active region (nMOSFET) remains without SiGe burial. This local differentiation applies the beneficial compressive stress effect only where needed (pMOSFET) while preserving the optimal characteristics of nMOSFET, thus improving hole mobility without compromising nMOSFET performance.
2Productivity
If gate electrodes are disposed at high density in one active region, then device integration is improved, but it becomes difficult to bury SiGe selectively in source and drain regions without affecting adjacent structures
Solution Approach 1:
The active region is segmented into first and second active regions with distinct processing paths. By dividing the structure before SiGe burial, the method enables high-density gate electrode disposition while maintaining selective SiGe burial capability in the first active region, as the segmentation provides clear spatial boundaries for selective processing.
Solution Approach 2:
The active region is divided into first and second active regions before SiGe burial is performed. This preliminary segmentation allows subsequent selective SiGe burial in the first active region even when gate electrodes are densely disposed, as the division is established beforehand to guide the selective processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the enhancement of hole mobility in pMOSFETs while maintaining nMOSFET performance by applying targeted stress through SiGe filling, thereby improving operational efficiency without degrading nMOSFETs.
Implementation Method 1
when SiGe is buried in a source and a drain region of a pMOSFET, a compressive stress may be applied to a channel region. As a result, the mobility of holes may be increased.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a first cap film over gate electrodes formed in a first active region and a second active region, etching the first cap film over the first active region, forming a second cap film over the gate electrodes formed in the first active region and the second active region, etching the second cap film over the first active region, etching the first active region using the gate electrodes to form concave portions in the first active region, and embedding a semiconductor material in the concave portions.