Selective Silicide Deposition for 3D DRAM Contact Resistance
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Solution Overview
Problem
The challenge in manufacturing 3D dynamic random-access memory (DRAM) cells lies in forming low resistance contacts, as traditional methods like PVD are not feasible due to non-line-of-sight properties and CVD reduces cavity volume, affecting capacitance.
Innovation Solution
A method involving the formation of a metal silicide layer on a semiconductor material layer, with a memory stack comprising sacrificial and alternating material layers, to create a low resistance contact by selectively depositing a metal silicide layer in a 3D DRAM active area, using a cluster tool system for precise processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If PVD is used to form metal silicide layer, then line-of-sight deposition is achieved, but non-line-of-sight properties prevent effective deposition in 3D DRAM structures
Solution Approach 1:
The patent replaces physical vapor deposition (PVD) with chemical vapor deposition (CVD) to form the metal silicide layer. This substitution allows the deposition process to occur through chemical reactions in the vapor phase, enabling conformal coverage of the 3D DRAM cavity structures that are inaccessible to line-of-sight PVD methods.
Solution Approach 2:
The patent changes the deposition method from PVD to CVD, fundamentally altering the physical and chemical parameters of the deposition process. This includes changing from physical sputtering or evaporation to chemical vapor phase deposition, enabling deposition in non-line-of-sight areas while maintaining silicide layer quality.
2Manufacturing precision
If CVD is used to form metal silicide layer, then conformal deposition in 3D structures is achieved, but cavity volume is reduced, affecting capacitance
Solution Approach 1:
The patent applies selective deposition only in regions where silicide formation is required (on the semiconductor material layer surfaces) while leaving the cavity volume largely preserved. The CVD process deposits silicide conformally on exposed semiconductor surfaces without significantly reducing the overall cavity volume, maintaining capacitance while achieving precise silicide layer formation.
Solution Approach 2:
The patent uses controlled CVD deposition to form silicide layers only where needed (partial action) rather than filling the entire cavity. By controlling deposition thickness and selectivity, the process achieves sufficient silicide coverage for low resistance contacts while minimizing impact on cavity volume and capacitance.
3Ease of manufacture
If traditional contact formation methods are used, then manufacturing simplicity is maintained, but low resistance contact formation fails in 3D DRAM structures
Solution Approach 1:
The patent segments the contact formation process into multiple steps: forming the metal silicide layer through selective CVD deposition, followed by capacitor and bit line formation. This segmentation allows precise control over silicide layer formation in the active area, ensuring low resistance contacts while maintaining overall manufacturing feasibility through systematic process breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-quality silicide layers with low resistance contacts, enhancing the performance of 3D DRAM devices by maintaining capacitance and reducing contact resistance.
Implementation Method 1
forming a metal silicide layer on a semiconductor material layer on a memory stack
Data Source
AI summary
Described are memory devices having a metal silicide, resulting in a low resistance contact. Methods of forming a memory device are described. The methods include forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side. A capacitor is then formed on the capacitor side of the metal silicide layer, and a bit line is formed on the bit line side of the metal silicide layer.