Selective Silicide Formation via Resist Etchback Masking
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Solution Overview
Problem
The miniaturization of semiconductor memory devices is hindered by the sheet resistivity of electrically conductive components, which can be reduced by forming metal silicides but may interfere with analog circuits due to undesirable junction leakage, requiring sophisticated manufacturing techniques for selective silicide formation.
Innovation Solution
A method involving the formation of a patterned mask layer on memory devices to selectively form metal silicides by preventing silicidation of underlying silicon-containing layers, using a metal layer that reacts only with uncovered portions, thereby reducing contact resistance and increasing conductivity without affecting adjacent components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal silicides are formed to reduce sheet resistivity, then conductivity of electrically conductive components is improved, but junction leakage increases causing interference with analog circuits
Solution Approach 1:
The patent applies local quality by forming silicide layers selectively on specific regions of the semiconductor device. Mask layers are used to prevent silicide formation on certain areas (such as analog circuit regions) while allowing it on other areas (such as digital circuit regions). This enables different regions to have different electrical properties - high conductivity where needed and low junction leakage where required.
Solution Approach 2:
The patent segments the device into different regions with different silicide formation characteristics. By using multiple mask layers and selective etching processes, the device is divided into zones that either receive silicide treatment or remain protected, allowing independent optimization of conductivity and junction leakage for each segment.
2Productivity
If device dimensions are scaled down to increase circuit density, then more bit cells per device are achieved, but sheet resistivity limits operating speed
Solution Approach 1:
The patent applies local quality by forming silicide layers selectively on specific regions of the semiconductor device. Mask layers are used to prevent silicide formation on certain areas (such as analog circuit regions) while allowing it on other areas (such as digital circuit regions). This enables different regions to have different electrical properties - high conductivity where needed and low junction leakage where required.
Solution Approach 2:
The patent changes the electrical parameters of conductive components by forming metal silicide layers. This transformation modifies the resistivity, sheet resistance, and overall conductivity of the affected regions, enabling faster signal propagation and improved operating speed in scaled-down devices.
3Object-generated harmful factors
If sophisticated manufacturing techniques are used for selective silicide formation, then junction leakage is reduced, but device complexity increases
Solution Approach 1:
The patent uses mask layers as intermediary materials to control the selective formation of silicide layers. These mask layers are deposited, patterned, and etched to define which regions will receive silicide treatment. The mask layers act as a mediating mechanism that simplifies the overall process by providing a clear, controllable method for achieving selective silicide formation without requiring complex direct control methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and increases the conductivity of bit lines and gate electrodes, addressing the challenges of miniaturization while preventing interference with other components, thus enhancing the performance of memory devices.
Implementation Method 1
forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer
Data Source
AI summary
Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.