Selective Metal Silicide Formation for Leakage Control
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Solution Overview
Problem
In integrated circuitry fabrication, conductive metal silicides can cause excessive leakage current to underlying substrate materials, necessitating selective formation of silicides in specific regions to prevent unwanted electrical connections.
Innovation Solution
A method involving a silicon-comprising substrate with distinct pairs of conductive structures and masking materials, where metal is deposited and annealed to form conductive metal silicides only between certain pairs of structures, avoiding silicide formation in other areas to control electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive metal silicides are formed in all regions, then electrical conductivity is improved, but leakage current increases
Solution Approach 1:
The patent applies local quality by forming conductive metal silicides selectively in specific regions rather than uniformly across the substrate. Different areas receive different treatments: some regions get silicide formation while others remain without silicides. This is achieved through selective masking and annealing processes that create spatially varying electrical properties, allowing high conductivity where needed while preventing leakage current in other areas.
2Reliability
If conductive metal silicides are formed to improve conductivity, then electrical connection is enhanced, but unwanted electrical connections are created
Solution Approach 1:
The patent segments the substrate into distinct regions with different electrical characteristics. By dividing the substrate into areas where silicides are formed and areas where they are not, the invention creates discrete electrical connection zones. This segmentation is accomplished through selective masking patterns and region-specific annealing, allowing precise control over where electrical connections occur and preventing unwanted connections in other segments.
3Object-generated harmful factors
If selective silicide formation is implemented to control leakage, then process complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-patterned masking structures that define where silicides will form before the annealing process. The masking layers are deposited and patterned in advance to create predetermined regions that will or will not receive silicide formation. This preliminary preparation simplifies the overall process by establishing the spatial pattern early, avoiding the need for complex multi-step selective annealing or post-processing adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise control of electrical conductivity, reducing leakage current and enabling targeted formation of silicides in specific regions, thereby improving the fabrication of integrated circuitry, memory circuitry, and field effect transistors.
Implementation Method 1
the substrate is annealed effective to react the metal with silicon of the substrate to form a conductive metal silicide
Implementation Method 2
react the metal with silicon of the substrate to form a conductive metal silicide
Data Source
AI summary
The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.