Selective Silicide Formation via Metal Layer Pre-Deposition

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Solution Overview

Problem

Existing methods for selective silicide formation on semiconductor wafers, such as the use of SiProt masks, face challenges including thermal incompatibility with 90nm and smaller technologies, stress creation in MOS transistors, and surface deterioration during etching, which lead to undesirable contact resistances and junction leakage.

Innovation Solution

A method involving the deposition of a metal layer followed by a mask layer, where the mask is patterned to expose only the regions not intended for silicidation, allowing for selective silicidation without degrading the wafer surface, and optionally using an amorphous silicon cap to enhance selectivity and reduce silicon consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a SiProt mask is used to prevent silicide formation on certain regions, then selective silicide formation is achieved, but the mask formation requires a thermal budget incompatible with 90nm and smaller technologies and creates stresses in MOS transistors

Engineering Contradiction:
Improveselective silicide formationVSAvoidthermal budget compatibility
Core Design Contradiction:
Manufacturing precisionVSTemperature

Solution Approach 1:

The patent applies preliminary action by depositing the metal layer before forming the mask layer. This reverses the conventional sequence where the mask is formed first. By having the metal layer in place beforehand, the subsequent mask patterning and etching steps do not expose the silicon surface to damage, as the metal layer serves as a protective substrate. This resolves the thermal budget compatibility issue while maintaining selective silicide formation capability.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If a SiProt mask is used for selective silicide formation, then contact resistance reduction is achieved on selected regions, but the etching process to remove the mask causes surface deterioration on regions intended for silicidation

Engineering Contradiction:
Improveselective silicide formationVSAvoidsurface deterioration
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The metal layer is deposited in advance before the mask layer is formed and patterned. This preliminary placement of the metal layer creates a protective interface during the subsequent mask removal etching process. The etching chemistry that removes the mask does not directly attack the silicon surface, thus preventing surface deterioration while still allowing selective silicide formation where the metal layer remains exposed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The metal layer acts as an intermediary protective layer between the silicon surface and the etching process. During mask removal, the etchant interacts with the metal layer rather than directly attacking the silicon surface. This intermediary protection prevents surface deterioration while maintaining the ability to form silicide selectively in regions where the metal layer is exposed.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If the SiProt mask is etched to expose regions for silicidation, then selective silicide formation is enabled, but the etching process leaves these regions vulnerable to attack resulting in undesirable surface deterioration

Engineering Contradiction:
Improveselective silicide formationVSAvoidjunction leakage
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The metal layer is deposited before the mask formation and patterning steps. This preliminary action ensures that when the mask is subsequently etched away to expose regions for silicidation, the silicon surface has already been covered by the metal layer. The etching process thus removes the mask without exposing the silicon to direct attack, preventing surface deterioration and reducing junction leakage, while still enabling selective silicide formation in the intended regions.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents surface degradation, reduces junction leakage, and improves compatibility with ultrashallow junctions and silicon-on-insulator technologies by ensuring precise control over silicide formation and minimizing silicon consumption from the junctions.

Implementation Method 1

depositing a metal layer on the slice (the metal being capable of forming a silicide by thermal reaction with the silicon), e) performing a heat treatment suitable for siliciding the metal deposited during step d)

Methodology Applied
Scientific EffectSilicidation: Chemical Bonding

Implementation Method 2

performing a heat treatment suitable for siliciding the metal deposited during step d)

Methodology Applied
Scientific EffectThermal reaction: Heat Treatment

Implementation Method 3

the exposed portion of the metal layer is removed (preferably by wet or dry etching) prior to the performance of the silicidation process

Methodology Applied
Scientific EffectEtching: Ablation

Implementation Method 4

said mask is patterned so as to cause only the metal in said first region to be exposed to said silicidation process

Methodology Applied
Scientific EffectPhotolithography patterning: Photopolymerisation

Data Source

PatentEP2074652B1Silicide formation on a wafer
Publication Date: 2011.05.11 NXP BV
  • EP2074652B1 patent drawingFigure 1
  • EP2074652B1 patent drawingFigure 2
  • EP2074652B1 patent drawingFigure 3

AI summary

A method of selective formation of suicide on a semiconductor wafer, wherein the metal layer (12) is deposited over the entire wafer prior to application of the SiProt mask (10, 16, 22) such that any etching of the mask (10, 16, 22) does not cause any surface deterioration of the silicon wafer.