Selective Silicide Formation for Low Resistance Contacts
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Solution Overview
Problem
The existing manufacturing processes for integrated circuits face challenges in forming low resistance electrical contacts between PMOS and NMOS field effect transistors, as the Schottky barrier height and contact resistance requirements differ significantly for each type, necessitating the use of distinct silicide materials.
Innovation Solution
The method involves forming first and second silicide layers on PMOS and NMOS FETs using different materials, such as nickel-containing layers for PMOS and titanium silicide for NMOS, through a process that includes depositing metal layers within contact trenches, annealing to form silicides, and using a hard mask for selective silicide formation to achieve low resistance contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same silicide material is used for both PMOS and NMOS FETs, then the manufacturing process is simplified, but the contact resistance cannot be optimized for both transistor types simultaneously
Solution Approach 1:
The patent applies local quality by using different silicide materials for different transistor types: nickel silicide for PMOS FETs and titanium silicide for NMOS FETs. This allows each contact to have the specific material properties needed for optimal electrical performance while maintaining a unified manufacturing process through selective area formation.
2Reliability
If different silicide materials are used for PMOS and NMOS FETs, then the contact resistance is optimized for each transistor type, but the manufacturing process complexity increases
Solution Approach 1:
The patent uses preliminary action by forming a hard mask pattern before depositing metal layers. The hard mask is selectively removed to expose only the desired transistor regions, allowing subsequent metal deposition and silicide formation to occur only where needed. This pre-patterned approach simplifies the overall process by preventing unwanted silicide formation rather than requiring complex selective deposition techniques.
3Reliability
If a hard mask is used for selective silicide formation, then the Schottky barrier height is optimized for each FET type, but additional process steps are required
Solution Approach 1:
The patent merges multiple functions into the hard mask layer: it serves as a pattern definition layer, a protective layer during metal deposition, and a selective removal template. By combining these functions into a single integrated process step, the patent achieves optimized Schottky barrier heights for both transistor types without requiring separate process sequences for each transistor type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of low resistance electrical contacts by optimizing the Schottky barrier height and contact resistance for each type of FET, enhancing the electrical connectivity between PMOS and NMOS transistors.
Implementation Method 1
annealing the first metal layer to cause the first metal layer to react and form the first silicide layers
Implementation Method 2
annealing the first metal layer to cause the first metal layer to react and form the first silicide layers
Data Source
AI summary
Methods for forming electrical contacts are provided. First and second FETs are formed over a semiconductor substrate. Openings are etched in a dielectric layer formed over the substrate, where the openings extend to source and drain regions of the FETs. A hard mask is formed over the source and drain regions of FETs. A first portion of the hard mask is removed, where the first portion is formed over the source and drain regions of the first FET. First silicide layers are formed over the source and drain regions of the first FET. A second portion of the hard mask is removed, where the second portion is formed over the source and drain regions of the second FET. Second silicide layers are formed over the source and drain regions of the second FET. A metal layer is deposited within the openings to fill the openings.