Self-Aligned Contact via Selective SiO2 Deposition
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Solution Overview
Problem
The scaling down of transistor gate pitch dimensions increases the likelihood of contact-to-gate shorts in MOS transistors, making it difficult to maintain accurate registration and critical dimensions, which are essential for preventing short circuits during the fabrication of contact plugs.
Innovation Solution
A method involving selective SiO2 deposition using a silanol gas in the presence of a metal-containing catalyst layer on a substrate, allowing for self-aligned contact formation without oxidizing or hydrolyzing agents, and repeating the coating and etching process to increase the SiO2 layer thickness on the dielectric surface while avoiding deposition on metal-containing surfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional overlay-driven patterning is used to form contact plugs, then the process is simpler and more established, but the likelihood of contact-to-gate shorts increases as transistor gate pitch dimensions are scaled down
Solution Approach 1:
The patent employs self-aligned patterning where the contact hole alignment is automatically defined by the gate structure itself rather than relying on overlay precision. The spacer formation process uses the gate as a template, ensuring that contacts are precisely positioned relative to the gate without requiring additional registration control
Solution Approach 2:
The patent performs preliminary spacer formation and material deposition before final contact hole etching. The spacer layers are deposited and patterned in advance to establish the contact alignment, ensuring that the critical dimension control is built into the structure before the actual contact formation occurs
2Manufacturing precision
If selective SiO2 deposition is used to form self-aligned contacts, then registration precision is improved and contact-to-gate shorts are reduced, but the process complexity increases
Solution Approach 1:
The patent utilizes selective deposition parameters where SiO2 is deposited only on dielectric surfaces at controlled temperatures (approximately 150°C or less) in the absence of oxidizing and hydrolyzing agents. This parameter control enables selective material formation that defines contact alignment without requiring complex additional process steps
Solution Approach 2:
The patent introduces an etch stop layer as an intermediary element between the SiO2 layer and the underlying structure. This etch stop layer facilitates the etching process by providing a clear termination point and enabling precise control of the contact hole depth, simplifying the overall fabrication process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the probability of contact-to-gate shorts by ensuring precise alignment and deposition control, enabling cost-effective scaling of transistor technology nodes without the limitations of conventional overlay-driven patterning methods.
Implementation Method 1
coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer
Data Source
AI summary
A substrate processing method for forming a self-aligned contact using selective SiO2 deposition is described in various embodiments. The method includes providing a planarized substrate containing a dielectric layer surface and a metal-containing surface, coating the dielectric layer surface with a metal-containing catalyst layer, and exposing the planarized substrate to a process gas containing a silanol gas for a time period that selectively deposits a SiO2 layer on the metal-containing catalyst layer on the dielectric layer surface. According to one embodiment, the method further includes depositing an etch stop layer on the SiO2 layer and on the metal-containing surfaces, depositing an interlayer dielectric layer on the planarized substrate, etching a recessed feature in the interlayer dielectric layer and stopping on the etch stop layer above the metal-containing surface, and filling the recessed feature with a metal.