Selective Solder Bump Formation on Wafer for Yield
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Solution Overview
Problem
In integrated circuit fabrication, forming solder bumps on entire wafers results in wasted costs and decreased assembly yield due to defective dies, which existing methods fail to address effectively.
Innovation Solution
A selective solder bump formation process where each die on the wafer is tested to identify known good dies and defective ones, with solder bumps only formed on the former, skipping the bumping process on defective dies to save costs and enhance yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If solder bumps are formed on the entire wafer, then the manufacturing process is simplified and production speed is maintained, but material waste increases and assembly yield decreases due to defective dies
Solution Approach 1:
The patent applies local quality by forming solder bumps only on specific regions (good dies) of the wafer rather than uniformly across the entire surface. The system identifies defective dies and excludes them from the bumping process, creating spatially varying properties where only functional areas receive solder bumps. This resolves the contradiction by maintaining high productivity through selective processing while reducing material waste by avoiding bumps on defective dies.
2Ease of manufacture
If solder bumps are formed on the entire wafer, then the manufacturing process is simplified, but cost increases due to wasted materials on defective dies
Solution Approach 1:
The patent implements preliminary action by performing wafer-level testing and identifying defective dies before the solder bump formation process. This advance identification allows the manufacturing system to plan and execute selective bumping, preventing material waste on defective dies. The preliminary testing and mapping of good versus defective dies enables cost-effective manufacturing by avoiding unnecessary material expenditure on non-functional areas.
3Stability of the object's composition
If solder bumps are formed on defective dies, then uniform processing is maintained across the wafer, but assembly yield decreases due to inclusion of non-functional dies
Solution Approach 1:
The patent applies dynamics by transitioning from a static, uniform processing approach to a dynamic, adaptive process. The system dynamically adjusts the bumping process based on real-time identification of defective dies through wafer testing. This dynamic adaptation allows the manufacturing process to respond to variations in die quality, selectively applying solder bumps only to functional dies thereby maintaining high assembly yield while preserving processing flexibility.
Data Source
AI summary
A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the wafer test performed. Solder bumps are formed on the KGDs.