Selective Spacer Deposition for Semiconductor Patterning
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in patterning target layers efficiently, leading to increased costs and device defects due to the need for etch processes that can damage underlying dielectric layers.
Innovation Solution
A selectivity-increasing process involving plasma treatment and self-assembled monolayers is applied to patterned layers, allowing for selective deposition of spacers along sidewalls without etching, thereby reducing the need for etch processes and protecting underlying layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If etch processes are used to pattern target layers, then patterning can be achieved, but underlying dielectric layers are damaged and device defects increase
Solution Approach 1:
The patent replaces the mechanical/chemical etching process with a deposition-based spacer formation process. Instead of removing material through etching, the invention deposits spacer material along sidewalls of patterned layers to define patterns, thereby avoiding damage to underlying dielectric layers while achieving the desired patterning precision
Solution Approach 2:
The patent introduces spacer structures as intermediary elements between the patterned layer and the target layer. These spacers serve as a mediating mechanism to transfer the pattern without requiring direct etching contact with underlying layers, thus protecting them from damage while maintaining patterning capability
2Manufacturing precision
If selective deposition is achieved through plasma treatment and self-assembled monolayers, then spacers can be deposited only along sidewalls, but process complexity increases
Solution Approach 1:
The patent applies plasma treatment and self-assembled monolayer formation as preliminary actions before the main spacer deposition step. These preparatory treatments modify the surface properties of patterned layers to enable selective deposition, achieving precise sidewall-only spacer formation through surface preparation rather than complex deposition control
Solution Approach 2:
The patent changes surface parameters (chemical composition, surface energy, wettability) through plasma treatment and self-assembled monolayer formation. These parameter changes create different deposition conditions on different surfaces, enabling selective spacer deposition along sidewalls while preventing deposition on top surfaces without adding significant process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces costs, minimizes damage to underlying layers, and decreases device defects by selectively depositing spacers only along sidewalls, improving the overall performance and reliability of semiconductor devices.
Implementation Method 1
The selectivity-increasing process may include performing a plasma treatment on surfaces of the patterned layer and the underlying dielectric layer
Implementation Method 2
forming self-assembled monolayers (SAMs) over the patterned layer and the underlying dielectric layer
Implementation Method 3
selectively depositing spacers along sidewalls of the patterned layer
Data Source
AI summary
Methods of patterning semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a first dielectric layer over a semiconductor substrate; forming a first hard mask layer over the first dielectric layer; etching the first hard mask layer to form a first opening exposing a top surface of the first dielectric layer; performing a plasma treatment process on the top surface of the first dielectric layer and a top surface of the first hard mask layer; after performing the plasma treatment process, selectively depositing a spacer on a side surface of the first hard mask layer, the top surface of the first dielectric layer and the top surface of the first hard mask layer being free from the spacer after selectively depositing the spacer; and etching the first dielectric layer using the spacer as a mask.