Selective Stress Enablement in IC Simulation Modeling
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Solution Overview
Problem
The integration of stress into semiconductor device simulations in integrated circuit design is computationally intensive, slowing down the design process due to current methods of implementation.
Innovation Solution
A method that involves converting integrated circuit representations into design shapes, adding control shapes to enable or disable stress modeling, extracting layout-dependent stress parameters, converting these parameters to stress parameters using a stress algorithm, and generating stressed device parameters through a compact model for simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If stress modeling is applied to all devices in the integrated circuit, then the accuracy of the simulation is improved, but the computational time and resources required increase significantly
Solution Approach 1:
The patent applies local quality by selectively enabling stress modeling only for specific devices that contain engineered stress elements (such as transistors with stressor structures), while excluding devices without such elements from the stress calculation. This localized approach maintains simulation accuracy for critical components while significantly reducing overall computational burden.
Solution Approach 2:
The patent segments the integrated circuit design into devices that require stress modeling and those that do not. By identifying and separating devices with engineered stress elements from the rest of the circuit, the system can apply computationally intensive stress analysis only to the necessary subset, thereby reducing total simulation time while preserving accuracy where needed.
2Reliability
If stress calculations are performed for all devices, then the reliability of the simulation is improved, but the computational resources consumed increase
Solution Approach 1:
The system applies local quality by directing computational resources only to devices with engineered stress elements. Devices without stress elements are processed using simpler, non-stress models, thereby maintaining simulation reliability for critical components while optimizing resource utilization across the entire circuit.
Solution Approach 2:
The patent implements partial action by applying stress modeling to only the subset of devices that require it (those with engineered stress elements), rather than uniformly applying it to all devices. This partial approach ensures sufficient reliability for stress-affected components while avoiding excessive resource consumption on devices where stress is not a factor.
3Manufacturing precision
If the design process includes comprehensive stress analysis, then the manufacturing precision is improved, but the productivity of the design process decreases
Solution Approach 1:
The patent applies local quality to manufacturing precision by performing comprehensive stress analysis only for devices with engineered stress elements, while using simplified models for other devices. This targeted approach maintains the necessary manufacturing precision for critical components without the productivity penalty of analyzing every device in detail.
Solution Approach 2:
The system segments the design process into stress analysis for critical devices and standard analysis for other devices. By dividing the workload this way, the patent maintains manufacturing precision where it matters most while improving overall design process productivity through reduced computational requirements.
Data Source
AI summary
A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design.