Selective Stressor Layer Etching for Strained Transistor Mobility
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Solution Overview
Problem
Current CMOS manufacturing techniques face challenges in achieving improved carrier mobility for both NMOS and PMOS devices without increasing manufacturing complexity or cost, as NMOS requires tensile stress while PMOS requires compressive stress, and existing methods often result in canceled stress effects when applied biaxially.
Innovation Solution
A method involving the selective etching of a stressor layer over the gate electrode in MOS transistors, using materials like silicon-rich nitride, nitrided silicon oxide, or silicon nitride to create either tensile or compressive stressor layers, depending on the transistor type, thereby optimizing strain conditions within the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a biaxial tensile stressor layer is applied to improve NMOS carrier mobility, then NMOS performance increases approximately twofold, but PMOS performance deteriorates or shows almost no improvement due to stress cancellation effects
Solution Approach 1:
The patent applies different stress conditions to different regions: NMOS devices receive tensile stress through tensile stressor layers, while PMOS devices receive compressive stress through compressive stressor layers or substrate structures. This localized differentiation allows each device type to receive the optimal stress for its carrier mobility enhancement without interfering with other device types.
Solution Approach 2:
The stressor layer is segmented by device type and location. Tensile stressor layers are selectively applied to NMOS regions, while compressive stressor layers or compression structures are applied to PMOS regions. This segmentation enables independent optimization of stress conditions for each transistor type within the same CMOS process.
2Reliability
If selective stressor structures are added to address both NMOS and PMOS requirements, then carrier mobility for both device types improves, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent merges the stress application step with existing CMOS manufacturing processes. Stressor layers are deposited using standard CVD or PECVD equipment already present in CMOS fabs, and the stress application is integrated into the existing process flow rather than adding completely new process steps. This reduces the incremental complexity of implementing selective stress for both NMOS and PMOS devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility for both NMOS and PMOS devices by precisely controlling stress conditions, improving device performance without adding complexity or cost to the manufacturing process.
Implementation Method 1
Stress distorts (i.e., strains) the semiconductor crystal lattice, and the distortion in turn affects the band alignment and charge transport properties of the semiconductor
Implementation Method 2
The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region
Data Source
AI summary
Embodiments of the invention provide a semiconductor fabrication method and a structure for strained transistors. A method comprises forming a stressor layer over a MOS transistor. The stressor layer is selectively etched over the gate electrode, thereby affecting strain conditions within the MOSFET channel region. An NMOS transistor may have a tensile stressor layer, and a PMOS transistor may have compressive stressor layer.