Selective TLB Invalidation in Multithreaded Data Processing

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The broadcast of TLB invalidate entry requests in multiprocessor systems is a high-latency operation that distributes requests to all processor cores, including those not caching the address translation, leading to inefficiency and increased bandwidth requirements as the system scales.

Innovation Solution

A data processing system with a master and multiple snoopers communicatively coupled via a system fabric, where the master selects a broadcast scope based on logical partition information to limit the distribution of multicast requests to only those nodes caching the address translation, reducing unnecessary broadcasts and improving latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If TLB invalidate entry requests are broadcast to all processor cores, then consistency of address translation across the system is maintained, but latency increases and bandwidth utilization increases

Engineering Contradiction:
Improveconsistency of address translationVSAvoidlatency of invalidate operation
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by making the broadcast scope selective rather than universal. The system identifies specific processor cores that cache the address translation entry to be invalidated and targets only those cores. This localized approach maintains the necessary consistency (reliability) while reducing unnecessary broadcasts to other cores, thereby decreasing latency and bandwidth utilization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the set of processor cores into two groups: those that cache the target address translation entry and those that do not. By segmenting the broadcast target set, the system sends invalidate requests only to the relevant segment (cores caching the entry), preserving consistency where needed while avoiding wasteful broadcasts to other segments, thus reducing overall latency and bandwidth consumption.

Inventive Principle:
Principle #1Segmentation

2Reliability

If TLB invalidate entry requests are broadcast to all processor cores, then all cached translations are invalidated, but bandwidth requirements increase as the system scales

Engineering Contradiction:
Improvecompleteness of invalidationVSAvoidbandwidth utilization
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system applies local quality by directing invalidate requests only to processor cores that actually cache the target address translation entry. This selective targeting ensures complete invalidation of cached translations (reliability) while minimizing the quantity of broadcast traffic (bandwidth utilization). As the system scales, the bandwidth requirement grows proportionally to the number of cores caching the entry rather than linearly with the total number of cores.

Inventive Principle:
Principle #3Local quality

3Reliability

If TLB invalidate entry requests are broadcast to all processor cores, then system-wide consistency is achieved, but processing efficiency decreases

Engineering Contradiction:
Improvesystem-wide consistencyVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the processor core population based on their caching status of the target address translation entry. By segmenting the target set and sending invalidate requests only to the relevant segment (cores that cache the entry), the system achieves the necessary system-wide consistency for affected cores while improving overall processing efficiency by eliminating redundant broadcasts to cores that do not need invalidation.

Inventive Principle:
Principle #1Segmentation

4Reliability

If TLB invalidate entry requests are broadcast to all processor cores, then all cores are updated, but the scope of distribution is excessive

Engineering Contradiction:
Improveupdates to all relevant coresVSAvoidscope of distribution
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system applies local quality by reducing the distribution scope from all processor cores to only those cores that cache the target address translation entry. This selective approach ensures that all relevant cores are updated (maintaining reliability) while minimizing the scope of distribution, thereby reducing system complexity and overhead associated with managing broadcasts to unnecessary cores.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240220418A1Selective distribution of translation entry invalidation requests in a multithreaded data processing system
Publication Date: 2024.07.04 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US20240220418A1 patent drawing
  • US20240220418A1 patent drawing
  • US20240220418A1 patent drawing

AI summary

A data processing system includes a master and multiple snoopers communicatively coupled to a system fabric for communicating requests, where the master and snoopers are distributed among a plurality of nodes. The data processing system maintains logical partition (LPAR) information for each of a plurality of LPARs, wherein the LPAR information indicates, for each of the plurality of LPARs, which of the plurality of nodes includes at least one snooper among the plurality of snoopers that holds an address translation entry for that LPAR. Based on the LPAR information, the master selects a broadcast scope of a multicast request on the system fabric, where the broadcast scope includes fewer than all of the plurality of nodes. The master repetitively issues, on the system fabric, the multicast request utilizing the selected broadcast scope until the multicast request is successfully received by all of the plurality of snoopers within the broadcast scope.