Multi-Core Memory Synchronization via Selective TLB Shootdown

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Solution Overview

Problem

Existing database systems that handle both Online-Transaction-Processing (OLTP) and Online Analytical Processing (OLAP) workloads are limited by scalability bottlenecks due to interactions with the operating system kernel and hardware platform, particularly in multicore environments, which prevents near-real-time OLAP analytics on top of OLTP databases.

Innovation Solution

A system for memory synchronization in a multi-core environment that allows selective translation lookaside buffer (TLB) shootdowns by assigning memory partitions to specific CPU cores and providing an interface for the database to control TLB shootdowns, reducing unnecessary interrupts and improving scalability through hardware-assisted virtual memory snapshotting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single database serves both OLTP and OLAP workloads using hardware-assisted virtual memory snapshotting, then resource utilization is improved, but scalability is limited by TLB shootdown overhead in multi-core systems

Engineering Contradiction:
Improveresource utilizationVSAvoidscalability
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system segments the address space by associating each memory region with a specific set of CPU cores through the cpumask field. This segmentation allows TLB shootdown operations to be targeted only to the relevant cores that accessed the modified memory region, rather than broadcasting to all cores in the system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements local quality by making TLB shootdown behavior dependent on the specific memory region being accessed. Each memory region has its own cpumask association, allowing the system to apply different shootdown strategies locally based on which cores actually accessed each region, rather than using a uniform approach for all memory.

Inventive Principle:
Principle #3Local quality

2Reliability

If TLB shootdown is broadcast to all cores to maintain consistency, then memory consistency is improved, but processing overhead increases

Engineering Contradiction:
Improvememory consistencyVSAvoidprocessing overhead
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the unnecessary TLB shootdown operations by identifying and removing cores from the shootdown target list that did not actually access the modified memory region. The cpumask mechanism allows the system to take out irrelevant cores from the broadcast, sending interrupts only to the subset of cores that need to be notified.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system uses feedback from memory access patterns to determine which cores should receive TLB shootdown interrupts. By tracking which cores accessed each memory region and storing this information in the cpumask field, the system can dynamically adjust shootdown behavior based on actual access feedback rather than using a static all-cores approach.

Inventive Principle:
Principle #23Feedback

3Productivity

If memory partitions are bound to specific cores, then TLB shootdown efficiency is improved, but system complexity increases

Engineering Contradiction:
ImproveTLB shootdown efficiencyVSAvoidsystem complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent uses copying by creating and maintaining cpumask copies in the kernel data structure that mirror the memory-to-core binding information. This copying approach allows the system to efficiently query which cores should receive shootdown interrupts without complex real-time analysis, as the binding information is pre-copied and stored in an easily accessible format.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS10452686B2System and method for memory synchronization of a multi-core system
Publication Date: 2019.10.22 HUAWEI TECH CO LTD
  • US10452686B2 patent drawing
  • US10452686B2 patent drawing
  • US10452686B2 patent drawing

AI summary

A system for memory synchronization of a multi-core system is provided, the system comprising: an assigning module which is configured to assign at least one memory partition to at least one core of the multi-core system; a mapping module which is configured to provide information for translation lookaside buffer shootdown for the multi-core system leveraged by sending an interrupt to the at least one core of the multi-core system, if a page table entry associated with the memory partition assigned to the at least one core is modified; and an interface module which is configured to provide an interface to the assigning module from user-space.